The Design Of Rapidly Fading Channel Simulator And Its FPGA Implementation

the rapid development of3G<E greatly increases the demand andcomplexity of research about wireless telecom equipment, where the system test andsimulation weigh more and more during the whole development cycle. In order toshorten time, the research personnel need test and simulate in various wirelesscommunication environment, where the wireless fading channel become an importantfactor during the research. Although the field testing in the real wirelesscommunication environment can directly reflect product quality, the result can’trepresent all for the trouble of equipment movement and the single local environment.To adapt to all kinds of wireless communication environment, a large number of fieldtests are needed, so the wireless channel simulator designed by features of variouswireless telecom environment is necessary for the wireless system research anddevelopment.The channel machine is expensive, while cheap and flexible FPGA chiphas been widely used at present. You can modify function in the way of softwareinstead of hardware,which can save much effort,so it is meaningful to realize achannel simulator based on FPGA. Currently, the flat fading channel is the foundationof all wireless fading channel simulation and modeling.Its stimulation methodsinclude sine wave superposition and forming filter. This article studies wirelesschannel’s characteristics of rapid changes and frequency selectivity in high speedmobile environment, which forges a foundation for developing the system of highspeed mobile wifi system. Firstly, this article introduces two methods for analogsimulation of rapidly wireless fading channel, including the improved model usingsine wave Jakes superposition and the model based on time delay line forming filter,which would be analyzed through comparison. Then channel simulator can beproduced to implement the algorithm by FPGA, in the way that the data will beuploaded and analyzed to host computer. During the implementation process, we takegreat advantage of matlab in processing data and DSP and IP core module in ISE.Harmonic in Sine wave superposition method uses IP core of DDS while Formingfilter uses Gaussian white noise module,which would be generated by matlab anddownloaded to ROM.To maintain randomness, pseudorandom sequence is producedby FPGA as the ROM address to call data. Due to complex function generated byfactors of forming filter, it is better to choose another way that factors could be generated in matlab and implemented by FIR filter, which can save logical resourceand reduce the complexity. The measured data and FPGA online logic analysis bothshow that the rapid changing channel simulator in FPGA introduced by this paper isin accordance with all characteristics of fast varying channel and completely satisfiedfor present experiment.