Design And Implementation Of MASH Sigma-delta ADC

The Sigma Delta ADC with oversampling technology and noise shaping technology has been widely studied as its advantages on easier to achieve higher resolution compared to the traditional Nyquist ADC and compromise in accuracy,speed and power dissipation.This paper focus on designing a MASH Sigma-Delta ADC.The Sigma Delta ADC mainly contains two parts:Sigma Delta modulator and digital decimation filter.According to the design requirements,the circuit structure and design parameters are determined by comparing the performance of different circuit structures.2-2 MASH structure Sigma Delta modulator with oversampling rate of 64 is designed,of which the integrator uses fully differential switched capacitor structure,and the first stage integrator uses chopper stabilization technique to reduce the 1/f noise.The full differential structure and gain enhancement technique are used in the operational amplifier.The quantizer is implemented by high speed dynamic latch comparator circuit.Considering the area and power consumption of the circuit,the digital decimation filter is implemented by Hogenauer cascaded comb filter(CIC filter)with decimation rate of 64 and cascaded number of 2.In this paper,the modeling and simulation of modulator and digital filter is realized by Simulink.And the circuit design and simulation is completed by tools of Cadence and Synopsys.The schematic and layout of Sigma Delta ADC are designed in MXIC 0.5?m CMOS Process.The ADC core area is 7.48 x 4.32mm~2.The voltage supply is 5V.According to the simulation results of the Sigma Delta ADC circuits,112.1 dB SNR and 17.1 bit ENOB are achieved under the condition of 1MHz sampling rate,64 oversampling ratio,and the signal bandwidth is 7.8kHz.All of the design specifications are fully met.