A Design Of Internal Power Amplifier For UHF RFID Reader

Radio Frequency Identification(RFID)technology is a new technology that utilizes radio wave to realize non-contact communication,identify specific objects and deal with related data.Usually,a RFID system is mainly composed of computer system,reader,antennas and tags.As a key module in the transmitter of reader,the performance of power amplifier is closely related to the quality of communication.Considering the configurable market requirements,this paper designs and simulates a power amplifier for Ultra High Frequency(UHF)RFID readers with CMOS process.This circuit can be configured into 2 modes: Mode 1.For fixed readers,the maximum output power should be large.This Circuit works as a power pre-amplifier,with external high-performance power amplifier.Thus the circuit just need to output a signal with small output power and high linearity.Mode 2.For mobile readers,the requirement of maximum output power is not very strict.The circuit outputs a larger power with worse linearity performance.This thesis introduces the basic principles of RF power amplifier,analyses and compares different types of power amplifiers,and briefly discusses the common linearization techniques.For the ASK modulation of UHF RFID system,two linear CMOS power amplifier circuits of different structure are designed and implemented: single-ended structure and differential structure.In the single-ended structure amplifier,a two-stage AB-type cascode structure is used,with input match and loadpull match,considered the parasitic inductance of the bond wire.Its results are as follows: saturated power is 21.3d Bm,the output 1d B compression point is 18.3d Bm,PAE efficiency at 1d B compression point is 24.3%.Based on the principle of single-ended structure amplifier,a differential structure power amplifier is then designed.Both the performance of output power and harmonic suppression effect are improved obviously.The results can be summarized as: an output 1d B compression point of 21.3d Bm,a saturation power of 22.9d Bm,a PAE efficiency at 1d B compression point of 30.7% and S11 less than-30 d B.In addition,the other auxiliary modules used in the circuit are designed.First,for the two design modes of the configuration,a two way ?-type resistance attenuators module is designed,either way controlled by digital signal for specific application.Then a reference circuit making use of positive and negative temperature coefficient parameters is designed.The simulation results of these two circuits basically meet the design requirements.In the end,layout design and matching considerations of RF circuits are discussed,and the pre-simulation and post-simulation of the whole circuit with tsmc 0.18?m RF CMOS process are completed.The pre-simulation results are good.However,the post-simulation performances are decreased,but basically satisfy design requirements.The results are as follows: mode 1 outputs 0d Bm with large power back-off;mode 2 can output 14 d Bm with less back-off,which has an output 1d B compression point of 17.55 d Bm.