Hardware Implementation Of Synchronization Between Nodes In Vehicular Ad Hoc Networks

Vehicular Ad hoc Network (VANET) is used to achieve the communications among vehicles or between a vehicle and an infrastructure, which plays an important role in the intelligent transportation system (ITS). It can effectively reduce traffic accidents and ease traffic congestion. VANET has a fast changing network topology, unstable wireless channel quality and limited network capacity. As such, it is very important to implement the fast and accurate synchronization among nodes in a VANET. This thesis presents a synchronization detection algorithm and gives the hardware implementation of the baseband receiver.Firstly, this thesis summarizes from three aspects, i.e. VANET, the synchronization technology in communications and FPGA. The research status of VANET all over the world is further illuminated.Secondly, the synchronization detection algorithm based on adaptive double-threshold criterion is put forward. The details include algorithm determination, preamble sequence design and synchronization detection algorithm implementation. The correlation operation and adaptive threshold technology are discussed comprehensively.Thirdly, the baseband receiver is designed. Based on the functional requirements, the overall structure of the baseband receiver is determined. Then a detailed introduction is made about the FPGA module, the ADC module and the DDR2 SDRAM module, including their functional characteristics and usage methods. On this basis, this thesis gives the specific circuit schematics of above and completes the PCB according to the specific requirements of each module in the work sequence and relevant knowledge of signal integrity.Finally, this thesis gives the design process of FPGA and shows the full processes of downloading programs to the hardware using iMPACT and debugging the hardware using ChipScope Pro. The important modules in hardware implementation of the synchronization detection algorithm, i.e. DCM, BRAM and FIR are discussed separately according to their functions and usages. Further discussions about test of ADC dynamic performance with FFT method and implementation of a DDR2 SDRAM controller with MPMC are executed.