Baseband Algorithms And Implementation Tech. For High-performance Navigation Receiver

As GNSS (Global Navigation Satellite System) is widely used all around the world, various fields have more requirements for navigation receiver, such as acquisition performance and multipath mitigation. Existing researches mainly pay attention to the algorithm for acquition and multipath mitigation. But quantitative analysis and optimized method combined with the restrictions of hardware implementation are developed in this dissertation, which is more directive for the design of navigation baseband chip.This dissertation is mainly focused on four crucial topics which restrict the promotion of the receiver's performance:1. Signal acquisition has the most computational complexity and maxim requirements for realtime processing in the navigation baseband processing, and its performance has direct influence on time to first fix, receiver sensitivity and some other key indexes. There is a lack of quantitative analysis of hardware complexity of acquisition methods in existing researches. Based on the uniform signal acquisition model, the hardware complexity and restrictions are compared between different aqutition methods, and quantitative analysis is presented. The systemic method of quantitative analysis is afforded to evaluate the implementation complexity of baseband chip.2. Pseudo-code phase error, carrier frequency offset and pseudo-code frequency offset will all give rise to serious deterioration of performance of acquisition, while traditional acquisition methods usually haven't dealt with the effects or compensated. Considering the coherent processing loss caused by pseudo-code phase error and carrier frequency offset, detection based on combinatory and judgment of adjacent detection limit is proposed, which can dramatically increase the probability of detection of system. Under the general conditions for the search step, equivalent signal to noise ratio of detectors can be maximally increased by 3.8dB. In view of pseudo-code frequency offset, an approach to compensating pseudo-code frequency offset based on decimation of signal fractional sampling is presented, so some engineering implementation problems caused by modification of frequency of sampling local codes are avoided. In the condition that the sampling rate is 5 times of code rate, the maximum pseudo-code frequency offset loss is less than 0.5dB and peak shift is also less than one tenth of chip width, being able to satisfy the requirements of most high dynamic capture systems. Based on this, a revised acquisition proposal on the basis of frequency domain of matched filter and FFT acquisition in parallel is put forward, and the design of matched filter and strategy of frequency search is also improved.3. Multipath effect is one of the main factors that affect the accuracy of position of navigation receivers. It is even the most primary error source in some application of high-accuracy survey. In consideration of the contradiction between performance of multi-path mitigation algorithm and resource consumption in navigation receivers with high performance, a multipath mitigation technique based on FIR model is put forward. Its performance is similar to that of MEDLL based on maximum likelihood estimate, but it has advantages that its computation complexity is independent of the amount of multipaths and hardware complexity can be reduced in the existence of multiple paths. As for implementation of high resolution multi-correlator, an implement architecture based on local pseudo-code differential is presented. Under the condition that correlator interval is one sixteenth of chip width, the computation and hardware scale is only one thirty-second and one eighth of traditional architectures respectively.4. A chip architecture based on the cooperation of multi-correlator is put forward, by establishing the multiple tasks model of navigation baseband processing. The conventional receivers which use single processor request a mass of resources, complicated scheduling and high realtime processing. Using the proposed architecture, multiple tasks are performed by multiple processors, so the shortcoming of the conventional receivers is conquered and the design of baseband chip is simplified. Also the chip is flexible and efficient simultaneity. In the view of some problems as the long consuming time and the heavy workload of simulation verification in chip development, simulation process based on Palladium simulation accelerator and prototype chip verification method based on FPGA is researched. These techniques are directly applied to developing the baseband chip. The above-mentioned reserchs are fully verified by actual tests in the aspects of power and performance.The researches have been used in Chinese autonomous satellite navigation system receiver and design of baseband chip and have obtained favorable effects in engineering application. Related methods and conclusions can also be applied in design of ranging receiver in other spread spectrum systems.