Design And Realization Of Digital Baseband Receiver For Bluetooth 4.0

With the rise of wearable devices and smart devices, Bluetooth low-energy technology has been widely used with ultra-low power consumption, long standby time, low-cost advantages. Bluetooth low-energy communication chip is the basis of this technology. Therefore, the design of Bluetooth low-energy digital baseband receiver has important significance.Poor judgment performance obtained by traditional carrier frequency offset compensation method and bit synchronization method because of the short preamble number in Bluetooth low-energy communication system. Firstly, the method of carrier frequency offset compensation based on preamble detection and symbol cumulative recovery is adopted. Only 4 to 6 of the preambles used, within the range of 190 kHz to -180 kHz of carrier frequency offset is compensated. Secondly, in view of the problem of the synchronization of the traditional bit synchronization algorithm under the condition of short preamble, the improved phase locked loop bit synchronization algorithm is adopted. The initial synchronization can be completed when the preamble is detected, which greatly increased the speed of bit synchronization. The Bluetooth low-energy digital baseband receiver algorithm is designed based on the improved carrier frequency offset compensation algorithm and bit synchronization algorithm, combined with digital down conversion and anti-image algorithm, GFSK direct phase demodulation algorithm. Finally the receiver is achieved by using Verilog language, and the optimization of the area and critical delay of the FIR filter circuit is made. In this paper, the RTL simulation of the whole receiver circuit is realized by Modelsim, and the function of the receiver is verified. At last, the code is synthesized by Design Compiler, with SMIC 130nm library used, and a total area of about 0.1 square mm is obtained.In the end, the design of FPGA functional verification and performance testing are designed. The result shows that at 8MHz clock, under the condition that the bit error rate is better than 0.1%, the digital baseband receiver circuit designed in this paper achieved the demodulation threshold less than 7dB, and the modulation frequency offset range between -160kHz and 100kHz can be tolerated, which meets the design goals.