Design And Implementation Of Digital Down Conversion Waveform Component Based On Multi-Core SIMD DSP

Software Defined Radio achieves a variety of wireless communication functions by loading different software waveforms on a common hardware platform,which is the key technology to radio communications and plays an important role in the field of military and civil communication.Currently the software defined radio device baseband architecture mainly consists of CPU,DSP,FPGA,which can adapt to ground,vehicle or aircraft communication equipment and other less demanding on the size and power consumption.With the wide application of mobile communication terminal,how to apply software defined radio technology to the size and power-constrained mobile terminal,so that supporting reconfigurable,upgraded,and other features,is the current hot research.In recent years,the emerging multi-core DSP can effectively improve signal processing capability,while reducing power consumption through parallel processing technology,has become a new way for software radio technology in the mobile terminal.In this paper,parallel design of software defined radio waveform components based on multi-core DSP is studied.Firstly,this paper studies the existing multi-core DSP architecture,in terms of VLIW architecture,SIMD architecture,and multithreading structure,Combined with multicore,multithreaded parallel processing technology,analyzing the advantages and prospects of applying the architecture to software defined radio mobile terminal.Secondly,digital down conversion is the waveform processing key components for high-speed radio communication signal processing.Demand for project design,combined with architectural features of SB3500,this paper proposes the basic characteristic analysis and related system parameters of a feasible DDC.Thirdly,this paper studied the SIMD instruction characteristics of SB3500 processor,designs and implements data-level parallelism of various basic components by aligned vector data,Q9 point quantifying,parallel program processing architecture.The results show that the overall average of DDC speedup is up to 38,some of the maximum speedup can reach 87.3,which greatly increasing the computing efficiency,demonstrating the huge advantages.Finally,in order to improve the degree of parallelism furtherly,multithreaded pipeline including division of tasks,load balancing,multi-threaded communication and memory allocation is studied,a method based on multi-threading technology in parallel DDC is proposed.