Design Of High Efficiency Time-to-Digital Converter Based On FPGA

Time-to-Digital Converters(TDC)is a time-interval measurement technique that can measure picoseconds and is widely used in high-energy physics experiments,quantum communications,laser ranging,and satellite navigation.There are many design methods of TDC,which are mainly divided into analog circuit method and digital circuit method.With the continuous development of digital integrated circuits,the digital circuit method design TDC performance is better than the analog circuit design method.The digital design method is divided into two categories,one is the TDC of the ASIC chip design,and the other is the TDC designed by the FPGA.The TDC of the ASIC chip design has stable performance and high measurement accuracy,but it is expensive and has a long development cycle.The TDC development cycle of FPGA design is short,the implementation cost is low,and the design is flexible.With the continuous development of FPGA chips,the level of manufacturing technology continues to increase.Compared with the TDC of ASIC design,the difference between performances is continuously reduced.Therefore,the realization of TDC on FPGA has important research significance.By comparing various methods,the conventional method improves the performance of time measurement,and the dead time becomes longer and the circuit logic resource consumption increases.In order to solve the problem of long dead time and high logic resource consumption,this paper chooses a combination of "coarse" counting and "fine" counting to design and implement a high efficiency TDC structure on Xilinx Artix-7 chip.On the one hand,this paper designs a new high-efficiency "fine" counting structure.In this structure,two clocks 180 degrees out of phase are used as the driving clocks of the D flip-flop array A and the D flip-flop array B,respectively,and the start signal or the end signal passing through a delay chain is simultaneously sampled,and finally the data will be obtained.Average the output as an output.The proposed "fine" counting structure can reduce the dead time and the consumption of logic resources and improve the measurement efficiency while ensuring its measurement performance.In the "fine " counting calibration module,the delay time of each delay unit is measured by the code density calibration method,which improves the resolution and accuracy of the measurement.On the other hand,the"rough" counting module uses a Gray code counter to reduce the counting error caused by the flipping of data multi-bits.The paper also built a TDC test system based on the nexys video development board.The test system includes a DDR3 controller module based on the Xilinx MIG core,a USB controller module,an 8-bit-32bit and 32bit-8bit bit-width conversion module,and a PC-side acquisition display software designed in QT and C++.Finally,a performance analysis of the improved efficiency TDC system was performed.The measurement results show that the average resolution of TDC is about 14.8ps,the differential nonlinearity(DNL)is(-0.72,1,09)LSB,the integral nonlinearity(INL)is(-4.28,0.21)LSB,and the measurement accuracy is RMS 24.6ps.The dead time is 5 ns,and the circuit logic resources are.reduced by about 25%.