A Novel Cache Hierarchy Based On Multi-retention STT-RAM Cells

At present,the spin-transfer torque random access memory(STT-RAM)is the most promising substitute of conventional SRAM cache due to its good scalability,high storage density and low leakage power.The area of one STT-RAM cell is only 1/3 to 1/9 that of SRAM,so we can achieve a much larger capacity with STT-RAM,thus improving the performance of cache system.Nevertheless,there are two drawbacks,namely,long write latency and high write energy,that limit its application in high performance cache hierarchy.To overcome these problems,we consider to relax the retention time of STT-RAM to optimize its write performance,and propose the novel cache hierarchy with multi-retention STT-RAM cells.Specifically,we implement the top level cache(L1 cache)with low retention STT-RAM,whose overall performance already exceeds that of SRAM.We also design a novel refresh scheme with low retention STT-RAM counter.The evaluation results show that compared with SRAM,the instruction per cycle(IPC)of low retention STT-RAM is 100.0% and its power consumption is 57.8%.For lower level cache,we propose to use multi-retention STT-RAM cells to construct the hybrid cache architecture,which is different for L2 and L3 cache.We also design its related data migration scheme to fully exploit the advantages of different STT-RAM cells.With the test results,it can be seen that the IPC of our multi-retention hybrid L2 cache is 98.6% that of SRAM,while its power is only 4.2%.The IPC of novel hybrid L3 cache is slightly lower than SRAM,at 99.4%,however,its overall power consumption is only 3.4% that of SRAM.