Research On NVM-based Hybrid Cache Architecture For 3D Chip Multiprocessors

With the development of multiprocessors,the demand for on-chip cache capacity is increasing.Traditional memory is facing increasingly serious problems such as low storage density and high static power consumption.The new non-volatile memory(NVM)has the characteristics of non-volatility,low leakage power and high density.It provides a new idea for on-chip cache design,but it also has many shortcomings,such as long write latency and large write power consumption.Therefore,the construction of a hybrid cache architecture based on NVM and SRAM is a more reasonable method for the design of multiprocessors.This paper studies the design of hybrid cache architecture based on NVM based 3D chip multiprocessors.In this paper,a simulation platform is built for hybrid cache 3D multiprocessors based on gem5,NVSim,McPAT simulation.We confirm the design idea of hybrid cache with STT-RAM by comparing the characteristics of NVM and traditional memory.Combined with factors such as power consumption,temperature,and access probability of different layout cache,this paper proposes a 3D chip multiprocessors hybrid cache layout strategy.By placing the SRAM layout at the center of the chip,the processor checks the low latency of frequent access to the cache intermediate bank.The static power consumption of the overall cache is reduced by placing the STT-RAM layout on the periphery of the chip.Compared with the architecture that has the same capacity of SRAM cache,the hybrid cache architecture using this layout strategy reduces the power consumption by 34%,and the performance is only reduced by 3.32%.Based on the layout of the hybrid cache architecture,we further study the problem of hybrid cache data migration in the 3D structure,and propose a data migration strategy for hybrid cache 3D chip multiprocessors.This strategy,by specifying the priority of data migration in different directions,keeping the migration information of the previous data migration,limiting the data migration of SRAM to STT-RAM,reduces the data migration jitter phenomenon of multi-core processors,and solves the problem of data migration failure in hybrid cache architecture.