Research On Hybrid Cache Architecture Generation And Access Mechanism For On-Chip Multiprocessors

As the number of cores in chip multiprocessors(CMP)continues to increase,the demand for cache capacity is increasing,so the power consumption overhead of traditional SRAM cache is increasing.The non-volatile memory(NVM)has excellent features such as non-volatile,near-zero leakage power consumption and high memory density,so it provides a new solution for on-chip cache design,but it also suffers from large write latency,large write power consumption and limited write lifetime.Therefore,building a hybrid cache architecture based on NVM and SRAM is a more reasonable CMP cache design method.This paper carries out the research on the generation and access mechanism of 3D CMP hybrid cache architecture.This thesis first establishes the power consumption,heat propagation and the durability model of NVM,and an optimization generation method for hybrid cache architecture based on STT-RAM and SRAM is proposed.The generation method determines the optimal capacity of each shared cache level under the constraint of the maximum temperature and NVM endurance of CMP,so that the system power consumption is minimized.Considering the influence of dark silicon,the optimal capacity of each cache level is allocated,and the power on and off state of each cache bank are determined to obtain an optimized cache bank layout.Based on the Gem5 simulation platform,the proposed generation method saves power consumption about 28.9% and improves the performance about 44.81% performance than that using SRAM as cache in the same area.Then a hybrid cache architecture dynamic generation scheme is proposed.This scheme monitors the current utilization and hotness of the cache bank and compares it with the corresponding threshold to determine whether it may be turned on or off.Then through priority judgment,it is finally determined whether the cache bank needs to be opened or closed.The paper also proposes to design a metric collector and a cache bank priority determinator to implement the dynamic generation scheme with lower hardware overhead.Through experimental simulation,compared with the fixed hybrid cache architecture,the cache architecture generated by the proposed scheme reduces power consumption by 14% and performance by only 6% degradation.Finally,a hybrid cache access mechanism is proposed.The access mechanism first analyzes the two types of cache lines,the dead line and the write burst line,and then optimizes the traditional access mechanism from three aspects.Through experimental simulation,in the case of using dynamic generation scheme,compared with the traditional writeback access mechanism,the proposed mechanism can improve the performance of the hybrid cache architecture by about 24.1% and save power consumption about 29%.