.0.13 ¦¬m In Ic Lithography Technology Platform Optimization And Lithography Resolution Enhancement Technology

With the increasingly development of the IC process, the key structure of IC is becoming smaller and smaller. The semiconductor ICs follow the roadmap that requires small volume high intensity high speed and low power dissipation. Nowadays IC has entered the ultra large semiconductor integrated circuits which brings technique phase from sub-micrometer to deep sub-micrometer.For the performance and reliability of the IC improvement, the process of the IC should be highly requested. Surely, as the key step of the IC manufacture process the lithograph is facing the giant challenge which is not only the solution to overcome the technique issue but also the amounts of money for equipment update.So there is a new subject that how to reach the process target without the process equipment update. The main solution is that modification of the hardware and optimization of the process condition. Especially the mainstream manufactory line inland are 8 inch techniques that are facing the technique level from 0.35μm to 0.11μm, the issue has more realistic meaning. The thesis introduce the regular RET(resolution enhancement technology), throμgh analysis and compare them, such as PSM OPC OAI and ARC.Meanwhile the thesis through the study of experiment data of the develop, try to cover the issue of the new process stage requirement by nozzle tip improvement and recipe optimize. In the end, we get the conclusion that the combination of LD nozzle and double scan recipe is the best solution to overcome the question. We also get many process factors that can keep process stable and controllable, for the need of 0.13μm process requirement andμse for the prodμct manufacture.