Toward Multiple Lithography Layout Decomposition DRC Tool

The Design Rule Check(DRC)tool is an important part of the physical design back-end EDA tool chain.It ensures the yield of chip production.With the development of semiconductor technology,the chips under advanced technology are becoming more and more dense.Conductor devices make multi-patterning a key technology in chip lithography production,and design rule checking for multi-patterning has also become an essential verification step in advanced processes.Whether the layout can be multi-decomposed is the verification object of the design rule check under the multi-layout decomposition,which determines whether the layout design meets the chip manufacturing requirements.This paper designs and studies DRC tools for the design rule checking requirements under multiple layout decomposition.Design rule checking in single-layer lithography layout mode is the implementation basis of design rule checking under multi-layout decomposition.This paper designs the running process of DRC tool in single-layer lithography layout mode.First,the DRC tool needs to initialize data,and in the data initialization stage,this paper designs a corresponding data storage structure for the DRC tool to undertake the layout design result information and process design rule information read from the DEF file and the LEF file,and then constructs the regionalized layout conductor graphic information storage through the R tree,so as to make The design rule checking tool has the ability of region query,which can quickly obtain the conductor inspection objects in the designated inspection region,which greatly improves the inspection efficiency.Completed data initialization With complete data support,the design rule checking tool implements checks for minimum width rules,minimum spacing rules,minimum area rules,minimum enclosed area rules,and short-circuit violations,and obtains design rules under single-layer lithography layouts test result.In the case of multiple lithography layout decomposition,because the layout decomposition will only increase the conductor spacing,the size and connection relationship of the conductors will not change,therefore,the check results of other design rules excluding spacing violations are consistent with the test results of design rules under single-layer lithography,and further examination was required to eliminate spacing violations between conductor patterns by layout decomposition.In this paper,the spacing violation between two conductor patterns is regarded as a conflict,and a conflict graph is constructed according to the conflict relationship between the conductor patterns,so as to transform whether the layout can be multi-decomposed into the coloring problem of graph theory,and then through the division and simplification of the graph The method decomposes and reduces the scale of the problem,and finally uses the backtracking method to check the coloring of the graph,that is,whether the layout can be decomposed multiple times,and finally obtain the design rule inspection result under the multi-lithography layout decomposition scenario.In the end,this paper tests the accuracy of the functions of the DRC tool through experiments,and compares the layout violation information recorded by the DRC tool with the actual situation of the layout through the layout viewer.