The Design Of Low Power Floating Point FFT Processor

As digital signal processing has many advantages,such as good flexibility,high accuracy,strong reliability and easy large-scale integration,etc.,it has now replaced the traditional analog signal processing in many fields.Fast Fourier Transform(FFT)plays a central role in a variety of digital signal processing algorithms,thus FFT processor has become the most fundamental and important unit in digital signal processing and it has been widely used in spectrum analysis,image processing,speech recognition,biomedicine,radar,filtering,wireless and cable communication systems and other fields.Furthermore,in the area of wearable and portable medical devices,such as portable blood glucose meter,electronic sphygmomanometer,heart rate detector,they require FFT processors with the characteristics of better flexibility,higher precision and lower power consumption.A low-power and configurable FFT processor is designed in this thesis,it can complete floating-point FFT computation of 4-point,16-point,32-point or 256-point as needed.By comparing the complexity of different algorithms and the influence on power consumption of hardware implementation structure,a frequency extraction of radix-4 FFT algorithm and memory-based single butterfly structure are used to accomplish the FFT processor.The design is optimized mainly in the structure level and the algorithm level according to the characteristics of FFT algorithm.The power consumption of the optimized butterfly structure is reduced by 41% by reducing the number of multipliers.A sentenced zero module is added to floating-point multiplier which is designed by improved Booth coding algorithm and a new symbol extension method,so that the power consumption decreased by 33%.The power consumption of the floating-point multiplier is dropped by 41% by adding a sentenced zero module.The storage unit is designed using the ping-pong structure and is block accessed,which can improve speed as well as reducing power consumption.The pipeline technology is used between the butterfly computation and reading and writing of storage units,as a result,its data throughput was improved.At the same time,the sleep mechanism is added to the design in the system level.When the module does not need to work,it enters the sleeping state to achieve the purpose of reducing power consumption.All the modules of the FFT processor are described in Verilog HDL language,and are simulated by Modelsim.Based on SMIC 0.18?m process library,the design is synthesized through DC,then the power consumption is analyzed by PrimeTime PX.Afterwards,layout and routing is done through ICC to generate the map and finally the imitation is completed.The test results show that the designed FFT processor successfully implements the computation of the 4-point,16-point,64-point and 256-point FFT,the computation error is less than 3.26 parts per million,the power consumption of 256-point is 32.5mW when the clock frequency is 100 MHz,which meets the requirements in aspects of speed,accuracy and power consumption.Finally the processor is verified on the ACX1329-CSG324 FPGA.The results show that when the clock frequency is 100 MHz,the power consumption of 256-point is 110 mW measured by Vivado.