802.11g N-system In The Design And Realization Of The Fft / Ifft Processor

The core technology of 802.11n is the MIMO(Multiple-Input Multiple-Output)- OFDM(Orthogonal Frequency Division Multiplexing), OFDM uses the FFT(Fast Fourier Transform)/IFFT(Inverse Fast Fourier Transform) to modulate and demodulate the data. FFT processor is the core data processing unit in OFDM system. In order to realize the wide application of OFDM, it has important practical value and application significance for 802.11n to design FFT/IFFT processor.In this thesis, I design a 64/128 point FFT/IFFT processer developed primarily for the application in a MIMO-OFDM multiplexing based IEEE 802.11n WLAN baseband processor. The parallel architecture of single butterfly is proposed to efficiently deal with streaming data flow. The proposed processor not only supports the operation of FFT/IFFT in 64 points and 128 points but can also config bits-width arbitrarily.In addition,it uses a improved butterfly unit can perform either one radix-4 butterfly or two radix-2 butterflies and needs less hardware resource compared with traditional four-parallel approach. Block Floating Point algorithm is used to increase the data dynamic range and solve the trouble of overflow, which costs same as fixed point algorithm but achieving better precision. The proposed processor is designed in a HJTC 0.18um CMOS process, the layout size is 2.04x1.96mm2, the core size is 1.35x1.27mm2. The highest clock frequency is 300MHz. The proposed processor requires only 48 clock cycles for a 64 points FFT/IFFT and 128 clock cycles for a 128 points FFT/IFFT.I design a reconfigurable high-precision FFT/IFFT processor. The whole design uses radix-4 serial architecture, reducing the system complexity and saving hardware resource. Present a improved block floating point algorithm which solves the overflow in long point FFT effectively and improves precision. The point can be configed for 64,256,1024 and the real and imaginary parts of data are 16 bits, the design not only can implement FFT, but also can implement IFFT. The proposed processor is designed in a SMIC 0.13um CMOS process, the area is 1.25x1.58mm2.At the highest clock frequency of 210MHz. The simulate result shows high-precision of the design.