Study On Configuration Data Analysis Of The Wireless JTAG Programmer

The technology is constantly breaking the digital world and the real world between the barriers,with the rise of virtual reality,artificial intelligence technology,this trend will be more obvious,and the field programmable gate array FPGA and complex programmable logic device CPLD will play a central role in the.The JTAG programmer on the market,FPGA and parallel CPLD programming in preference to slow loading,and the PC machine has almost eliminated the parallel port,has been difficult to meet the needs of developers.Different from the current market of programmable logic device download device,the design of the JTAG download device,to avoid the PC configuration tool for the design,can be compatible with the official Altera configuration tool QuartusII.In addition,JTAG programmer in the design of the SPI interface is used to simulate JTAG data transmission,accelerate download speed.This paper focuses on the configuration data in the analysis technology of wireless JTAG programmer.Around this point,will elaborate the related technology of JTAG programming: boundary scan test technology and JTAG protocol,the basic structure and boundary scan test instructions including boundary scan logic set;USB bus transmission technology.In order to realize the configuration function of JTAG wireless programming programming,through in-depth analysis of communication mode of JTAG programmer configuration process and system structure,the overall design of JTAG programmer.The design of a series of theoretical basis and the overall scheme based on the USB-Blaster programmer Altera official as the research object,according to the configuration process of the programmer,internal communication mechanism and configuration process of timing design a series of program analysis JTAG programmer.According to the configuration process of Altera waveform from the USB-Blaster analysis of acquisition and comparison,the internal state machine design of JTAG programmer.In order to improve the speed of loading configuration JTAG programmer,designed a simulation program using SPI JTAG data transmission interface.And using FT245 RL and STM32F205RGT6 as the main chip,according to internal state machine JTAG programmer and SPI simulation JTAG interface program,the internal state machine design JTAG conversion program.Debugging of each module,integrated debugging,to achieve their respective functions,complete the JTAG programmer platform design,Download verification.The JTAG programmer and the development trend of the JTAG programmer made a discussion and expectation.