Design And Simulation Of JTAG Controller In FPGA

FPGA (Field Programmable Gate Array) provides great deal of programmable logical resource. Users implement various applications on FPGA chip after downloading the configuration bit-streams which are designed for their specific application requirements. JTAG (Joint Test Action Group) is an essential component of FPGA chip. It specifies a boundary scan register chain and the corresponding TAP (Test Access Port) controller around the periphery of a chip. Nowadays JTAG circuit is designed in almost all FPGA chips. The main objective of JTAG circuit is to test both internal logical functions and external pin interconnection of chips. In addition, it also provides In-System programing capabilities. Therefore, with JTAG circuit provided test capability and easy to use programming, it promotes the development and application of FPGA. This thesis designed a JTAG controller circuit module. This project is a sub-project of FPGA chip design project from Xi’an Intelligence Silicon Technology Limited Company. The main content of this thesis includes following.1. Using Verilog Hardware Description Language to design Register-Transfer-Level JTAG controller and boundary scan test logic. This design conforms to the IEEE (Institute of Electrical and Electronics Engineers) 1149.1 standard. This JTAG controller can achieve all kinds of test mode defined in the IEEE 1149.1 standard and different test logical functions in each test mode. This JTAG controller circuit module includes following sub-module:(1) State controller module, including TAP controller of JTAG and state machine of In-System-Program; (2) Instruction register and instruction decoder module; (3) Test data register module, including bypass register and IDCODE register.2. State machine module and corresponding instructions system, controlling In-System-Programing function, are also included in this JTAG controller. The logical function of this part, which can program FPGA in system, conforms to the IEEE 1532 standard, and it enhanced the flexibility of FPGA. In addition, instruction system used to control embedded eFlash and SRAM (Static Random Access Memory) module in FPGA is contained, which can be used to cooperate with the In-System-Programmable functions.3. Test bench corresponding to the circuit module was designed, and functions simulation corresponding to the circuit module was also implemented. The result of simulation indicated that the circuit module achieved all expected logical functions, which verified the correctness of the logical functions of the circuit module. After the designing and simulating finished, synthesis was also implemented and the result indicated all of register-transfer-level code can be synthesized to generate circuit.4. Selecting simulation path according to the timing parameters of design target and designing wire models by measuring wire length in layout, based on which, simulation circuit was designed and primary timing parameters simulation corresponding to the circuit module was also implemented. The design conforms to design target based on the comparison between timing simulation results and design target. Layout for circuit module was designed and post-simulation was also implemented in order to ensuring that the layout was correct. Chip level functional test was implemented, which ensured that designed circuit module can implement logical function correctly in the chip.Above all, the designed register-transfer-level circuit module can provide the FPGA with a JTAG controller with correct logical function and be synthesized to generate circuit, the performance of circuit module conforms to the design target, and the circuit module can implement logical function correctly in the chip. That is to say, the expected goal of the thesis was achieved.