Research On Decoding Algorithm And Hardware Implementation Of Polar Codes

Polar codes are the first known channel coding method which can be strictly proved in theory to reach the channel capacity.Due to their explicit structure and low-complexity encoding / decoding algorithm,polar codes have become a research hotspot both in academia and industry.In recent years,through the efforts of channel coding scholars,polar codes can achieve a better error correcting performance than widely used Turbo and LDPC code.Because of the superior performance,low encoding and decoding complexity,polar codes will have a broad application prospects in the future of digital communication systems.Based on the deep understanding of channel polarization and polar coding theory,this paper studied the polar codes' code construction method,the enhancement decoding algorithm,the quantization scheme and the hardware implementation of the CRC-Aided SCL decoder.The research work of this paper mainly includes the following aspects.Firstly,the code construction methods of polar codes are studied.Several common code construction methods are described,and the complixity comparison result of diffirent code construction method are given.The performance simulation results of two kinds of code construction method based on Bhattacharyya Parameter and Gaussian Approximation are proposed.It can be found that Gaussian Approximation method can obtain better decoding performance and the complexity is not changed compared with the Bhattacharyya Parameter method.Secondly,the enhanced decoding algorithm and quantization scheme of polar codes are studied.The successive cancellation list(SCL)and CRC-Aided SCL decoding algorithms are studied,and the simulation results show that the decoding performance of the SCL decoding algorithm increases with the increase of the list size.However,when the channel condition is good,the SCL decoding algorithm cannot bring continuous performance improvement with the increase of list size.The CRC-Aided SCL decoding algorithm will bring continuous performance improvement when the list size increases,and the larger the list size,the greater the performance gain.The quantitative scheme of CRC-Aided SCL decoding algorithm are studied,and the simulation results show that used 8-bit for LLR and 12-bit for Path Metric can achieve a similar decoding performance to the floating-point scheme.Thirdly,the hardware implementation of the CRC-Aided SCL decoder is studied.A hardware implementation architecture of CRC-Aided SCL decoder with high performance and low complexity is proposed,and the concrete realization method and simulation result of each sub-module are given.The hardware implementation results show that the average decoding delay of the CRC-Aided SCL decoder is 0.159 ms at 300 MHz,and the average decoding throughput is 3.22 Mbps,and the hardware complexity is low.