Theoretical Analysis Study And Hardware Implementation Of The Polar Codes Decoding Algorithm

Polar codes is a new type of channel coding based on the phenomenon of channel polarization,which has the characteristics of shannon limit available and low complexity of encoding and decoding.It has been used in the coding scheme of 5G control channel by 3GPP the international mobile communication standardization organization.Compared with the Low density Parity check code(LDPC),Polar codes' main decoding algorithm,Successive Cancellation(SC)decoding algorithm,has the long-latency disadvantage,that can't meet the to the requirements of future communication system for high throughput and low latency.Therefore,how to reduce the latency and improve the throughput is an urgent problem to be solved.This paper focuses on the vital issues such as the Polar codes decoding algorithm and the design of the decoders for Polar codes.The paper is organized as follows:1.Starting from the channel polarization phenomenon,the specific process of channel polarization and Polar codes construction is introduced,laying a theoretical foundation for the subsequent research on Polar codes decoding algorithm.Firstly,channel combination and channel splitting are analyzed.Then the reliability measurement method of polarization channel is described.Finally,the method of constructing code words and selecting reliable polarization channels for BEC channel is given.2: In order to reduce the latency,the paper proposed the Multibits Decision Simplified Successive Cancellation(MD-SSC)decoding algorithm based on the Simplified Successive Cancellation(SSC)decoding.By analyzing the SC decoding algorithm,we found that the decoding process corresponding to a large number of continuous frozen bits is inefficient.In order to solve this problem,we divide the single codeword into frozen bits partial code,information bits partial code and mixed bits partial code,in which mixed bits partial code occupies a considerable part of latency.By adopting multi-bits decision on the high latency parts of SC decoding,the total number of decoding decisions in the SC decoding process can be reduced,thus reducing the decoding latency.The simulation results show that the decoding latency can be reduced by this method,and can be further improved as the code length increases.3: In order to optimize SC decoder hardware structure and improve its throughput,a high-throughput SC decoder based on pipeline structure is designed.Firstly,starting from the basic hardware structure of SC decoder,the activation state of each module in the decoding process of the hardware structure is analyzed,and it is found that the traditional SC decoding structure has the problems of long idle time of decoding nodes and low hardware utilization rate.In order to improve the utilization of the internal modules of the decoder,a structure with f decoder node and g decoder node working as independent modules is designed.Subsequently,SC decoding process is subdivided into multiple stages,and then pipeline parallel operation is used to each decoding stage,which can improve the decoder throughput.Finally,the FPGA design of SC decoder is implemented based on pipeline structure.Simulation result shows that the decoder can reach the throughput of 1.06 Gbps with the 133.33 MHz system clock.