The VLSI Architecture Design Of Arithmetic Coding For RDO And WPP-Based Parallel Entropy Coder In HEVC

HEVC is the new generation video coding standard released by JVT(Joint Video Team)in 2013.HEVC adopted a serial of new technologies and could achieve compression efficiency improved 50% compared with H.264/AVC,but it also increased the implementation complexity of the video encoder.The entropy encoder of HEVC is CABAC.It has strong data dependencies,which makes it the bottleneck of the hardware implementation of the video compression system.This paper first analyzed the function of CABAC in HEVC based on the study of the principle of CABAC sub-modules.One for the calculation of the RDO(Rate Distortion Optimization)to complete the division decision of the coding unit,and the other for the output of binary bitstream.Based on the analysis of the algorithm of CABAC,this paper proposed a fast algorithm of arithmetic coding for RDO,using the length of the bin string obtained by binarization instead of the length of bitstream to calculate RDO.This paper designed the hardware architecture based on the proposed algorithm,and studied and solved the problem of coefficient scanning dependency during the implementation process.The fast algorithm proposed simplified the architecture design of the entropy encoder in the case of less performance loss of the video compression system,and saved the hardware resource cost.This paper analyzed the data dependency in the context modeling and arithmetic coding process,and implemented the architecture design of the context modeling module and the arithmetic coding module.Then the parallelization technology WPP in HEVC was introduced in entropy coder to allow parallel coding of multiple CTU lines.Finally the architecture design of a WPP-based parallel entropy coder was implemented based on the context modeling module,the arithmetic coding module and the WPP,which improved the parallelism and data throughput of the entropy coder.The design is synthesized with 65 nm CMOS technology and can work at a speed of 400 MHz.The design can meet the speed requirement of 4Kx2K@60fps and can be used for real-time coding of the high-definition video.