Design Of The Key Modules In HEVC Intra Codec

High Efficiency Video Coding(HEVC)will serve as a new generation of digital video compression standards.Its aim to to double the compression efficiency compared with H.264.However,the efficiency is improved and the complexity is greatly increased.Therefore,how to reduce the complexity and improve the codec speed,while reducing the use of hardware resources,has become a research hotspot.In this paper,three modules of DCT transform,quantization and CABAC decoding are designed to optimize the design of the hardware circuit in terms of reducing the hardware area and improving the coding speed.Specifically as follows.HEVC using fixed-point integer transform technology,the maximum size of the transform block up to 32x32,if the direct implementation will have a lot of integer multiplication and addition operations.So this paper uses part butterfly algorithm of reducing the number of operations of multiplication and addition,on the basis of the even part of a high degree of parallelism with the local systolic array to achieve,in order to reduce the critical path delay.And the multiplication of the realization of the use of sub-multiplexing shift addition and subtraction to achieve,in order to further reduce the size of the area by the multiplication operator.The results show that the optimized circuit can work at the frequency of 205MHz.For 4,8,16,the size of the block size,the calculation of 32 points 1-D DCT transform cycle is used for 3,5,8,9?Optimization of each parameter in the quantization process.The variable MF and QP%6 in the process of quantification,the total number of TT_Shift mobile and M,floor(QP/6)relationship is designed to form,avoid the remainder and divide operations,improve the speed of access to MF and TT_Shift.For variable f,in order to avoid the decimal operation,also makes rounded operation.Subdivision of the variables,so that the quantization process is optimized.Comprehensive results show.The circuit can work at the frequency of 223 MHz and has the advantage of time and area.Because of the dependence of each element in the entropy decoding,the data throughput of CABAC decoder becomes the bottleneck of decoding,and there is a large path delay in the regular decoding module.In order to solve this problem,In this paper,we propose a CABAC decoding scheme which can decode two bits simultaneously,and insert the pipeline register to save the candidate context model in order to reduce the critical path delay.In the decoding of the current bin,by comparing the offset and the length of the decoding interval to determine whether the decoding of the MPS symbol,so as to predict the next bin decoding context and decoding interval.The results show that two bin can be decoded simultaneously in one cycle,and can be operated at 125.5MHz frequency.All of the design by Verilog HDL RTL,the results show that the three module improved without obvious influence the image quality calculation speed is improved,the resource area has been optimized.