The Research On The Layout Dependent Effect Based On 40nm Process

With the reduction of the size of the process,a variety of layout dependent effects are introduced in the nanometer process,These layout dependent effects have become important factors of causing internal fluctuations in the chip.These layout effects will affect the carrier mobility and the device threshold voltage,resulting the changes in device performance,and also the circuit performance changed.How to deal with the layout effects in the nanoscale process has become an unavoidable problem,so the influence of these layout effects must be taken into account in the device and circuit design.In this paper,the performance of devices with different layout proximity effects in 40 nm process are studied,and the influence of the layout effects on the circuits is also illustrated,which provides the basis for the modeling of the device and the design of the nanometer circuit.In this paper,the influence of the layout depedent effects on the device and the circuit are studied based on the SMIC 40 nm process.The test structure of the device is composed of STI group,STIW group,dummy gate group and contact hole effect group.The results of the test results are analyzed and explained.The test results show that the environment around the layout and its layout changes will affect the performance of devices,and the threshold voltage and saturation current are analyzed and explained by the trend of the different layout effects.And then further study the impact of circuit performance about the circuit in the key components of the layout effects.The layout of the different inverters have been studied and it has been found that the power delay is minimized when the SA / SB parameters of the NMOS device are increased and the number of dummy gate is 3 in the layout of the inverter;The influence of the NMOS differential pair in the circuit is studied for the comparator circuit,The simulation results show that,The layout dependent effects of the critical devices in the comparator circuit will change the performance of the circuit to a certain extent;The influence of the PMOS differential pair device and the NMOS current mirror device is also studied for the regulator circuit,and the regulator circuit for chip and probe testing,the test results show that,the output voltage and bias voltage of the regulator vary depending on the layout parameters,and the larger the SC,the closer the test results are to the simulation results,the greater the SA / SB,the more stable the voltage.The circuit performance is improved by appropriately increasing the SA / SB of the NMOS device without affecting the area,and the well of the critical device is as far away as possible from the channel.