Analysis And Optimization Of Lithography Effects Caused By Dummy Fill

With the continual shrinking of technology nodes, lithography issues put obstacles in the way of Moore’s law, abstracting most concerns of semiconductor industry. Litho-related design for manufacturing (DFM) has been widely used in nanometer scale. In addition, the development of VLSI and SoCs makes metal density problems more complicated. Traditional solution to metal density is to insert dummy fill, to improve the wafer topography after CMP process. However, dummy fill not only deteriorates electrical parameters of design, but also has influence on lithography variations of original patterns. Wafer topography introduces new variation into defocus value in lithography process, which will no longer be negligible owing to worsening of wafer topography and litho effects.This paper has analyzed litho effects caused by dummy fill, starting with the relationship of lithography variation and wafer topography after CMP. To realize the more accurate prediction of litho variations, we proposed a localized defocus-aware litho simulation methodology applied in full chip, for accurate prediction and analysis of litho hotspots brought by dummy fill. And in the light of previous assessment, to optimize the litho effects caused by dummy fill, a new defocus-aware dummy fill methodology is presented, which attempts to make a tradeoff between chip topography and litho variations of original pattern.The result indicates this method doesn’t increase the amount of litho hotspots of original routed layout, while decreasing the range of CMP thickness variation effectively. Reduction of M3is30.3%, and M4is38.6%on the range of wafer topography. Comparing with traditional metal fill methodology, the amount of litho hotspots is reduced dramatically which means less OPC wok and shorter turn-around time(TAT). This work will have great significance to DFM related research in future.