Characterization and modeling of the dummy gate (field plate) bias effects in RF silicon LDMOSFETS

The effects of voltage bias on the dummy gate (also called field plate) of Si LDMOSFETs are investigated. Numerical 2-D simulations on dummy-gated LDMOSFETs are used to understand and explain the influence of dummy gate bias on LDD resistance, quasi-saturation, mobile charge, electric field profiles, internal drain potential, I-V curves and breakdown voltage. The functional dependences observed from these simulations are incorporated into a modified BSIM4 model that accounts for the drift region in LDMOSFETs, as well as the effects of dummy gate bias on DC and RF performance. The model is extensively validated with DC I-V, bias dependent S-parameters, and non-linear large signal RF measurements, and simulated results show good agreement with measured data.; Numerical simulations show that with increasing positive bias on the dummy gate, electrons are pulled closer to the semiconductor surface and the on-resistance and quasi-saturations effect in the LDMOSFET is reduced. This leads to an improvement in I-V characteristics and an increase in maximum saturation current, which was observed in measurements and well predicted by the model. The improvement comes with no sacrifice to the breakdown or snapback voltage for dummy-gate voltages below 20 V. However sustained positive bias on the dummy gate increases hot-carrier-injection and leads to a faster degradation in on-resistance, an effect that was well characterized experimentally.; The reduction in on-resistance and quasi-saturation allows a larger swing of RF voltage and current on the drain terminal. This leads to an increase in the maximum RF power and efficiency as well as an improvement in linearity, a result which was experimentally characterized and well predicted by the model. This demonstrates that the performance of LDMOSFET based PAs (which are typically used in cellular base-stations), can be significantly improved by appropriate voltage biasing of the dummy gate.; The knowledge and circuit model developed in this work is applied in the design of an adaptively biased power amplifier, which combines adaptive biasing of both the drain and dummy gate to achieve improved performance in power and efficiency of the power amplifier.