Look Up Table Based Parasitic Capacitance Extraction Method For CMP Dummy Fills

With the development of integrated circuit manufacturing technology, CMP is widely used as a wafer planarizing technique. Although the CMP technology has relatively good planarization, but due to the non-uniform of lower layout graphical density ,there will still be a polished uniform dielectric thickness. Using metal dummy filling technology effectively alleviates the problem, but the coupling capacitance due to this technology has an important impact on circuit performance and yield.In order to solve these problems in dummy fills insertion , there are three aspects been studied in this paper which includes fill area,fill mode optimization and parasitic capacitance extraction. A optimization algorithm of computing the security regions for dummy fills was proposed , and then the main parameters of diamond fill patterns were studied. Then based on these work a lookup table based algorithm on calculating the increment of diamond fill mode coupling capacitance was proposed.The algorithm is fast, high precision and versatility, and can be used for parasitic capacitance extraction and performance optimization in the design process of dummy fills.