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Dummy Fill Copper Interconnect Synthesis Algorithm Research

Posted on:2013-04-03Degree:DoctorType:Dissertation
Country:ChinaCandidate:P WuFull Text:PDF
GTID:1228330395451554Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
It is the great improvement of integrated circuits (IC) that leads us to the information society and personal life of today. From the birth of the first semiconductor device to the integration of almost billion transistors on a single chip, the fabrication technology and design methodology of IC have varied much in just a few decades. The technology node of IC fabrication continuously scales down from microns to nanos. The lithography and chemical mechanical planarization (CMP) processes show significant dependencies on layout patterns in the advanced fabrication, and cause variations of feature size in horizontal and vertical dimension respectively. These variations finally influence the chip performance and functionality. Nowadays, the process variation and manufacturability have become critical issues that dominate the performance and yield of IC and are the main concerns in the new design methodology.Dummy fill is a key technology in the new generation of design methodology, i.e., design for manufacturability (DFM) and design for yield (DFY). Its most important application is copper interconnection. It improves the layout pattern distribution and further reduces the process variations by introducing in some non-functional metals in the previous design. The key process of dummy filling is to determine the fill amount on any specific position of the layout with various constraints, i.e., fill synthesis. The study of this work thus focuses on the efficient algorithms of fill synthesis. The major contributions of this work are listed below.Firstly, a new fill synthesis problem considering the pattern density gradient constraint along with density range and fill amount is proposed, as well as an efficient iterative method based on the CLP and its fast approximation scheme. The influence of pattern density gradient on the manufacturability and yield of IC has been more and more significant. But the traditional dummy fill methods only consider the density range while cannot constrain the gradient effectively. The fill method proposed in this work takes both the density and gradient into consideration and minimizes the total fill amount. An iterative flow is designed to solve the gradient-aware fill synthesis problem based on the fast solver of covering linear programming (CLP), and some heuristic technologies are innovated to improve the convergence. Comparing with the traditional linear programming (LP) algorithms, this method reduces the time complexity of the problem from O(n3) to O(n2logn). The performance of this proposed method is analyzed and verified by theoretical analysis and numerical experiments respectively.Secondly, another method based on hotspots clustering and subproblems solving in local areas is proposed for the gradient-aware fill synthesis problem. This method for the first time takes the characteristics of layout pattern distribution into account of the fill synthesis optimization process. Observing that the gradient hotspots appear in clusters usually, this method firstly clusters the hotspots into groups and then solves the subproblems in local areas taking the advantage of the high efficiency of LP solving in small-scale problems. This method improves the previously proposed iterative method both in precision and speed, demonstrating good performance in practical applications.Besides, this work takes some preliminary study of the model simulation based fill method. As the increasing requirement of fabrication precision in the IC industry, the density rule-based fill method has been challenged. The fill method based on model simulation that takes account in more pattern characteristics and fabrication process is supposed to be the future of dummy fill. A fill method based on a two-level simulation: the rigorous chip scale simulation and fast local simulation is proposed in this work. The preliminary experiments and analysis show that the proposed method improves the variance of chip topography over50%with the same fill amount compared with the traditional rule-based fill.
Keywords/Search Tags:design for manufacturability, dummy fill, density gradient, efficientsynthesis method, covering linear programming, hotspots clustering, model-based fill
PDF Full Text Request
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