Design And FPGA Implementation Of CCSDS-Turbo Codes With Low Memory

Turbo codes, which have been proposed by the French scholar C.Berrou in 1993, have attracted great interest in the industry due to its excellent performance near the Shannon limit. The Turbo code has become a popular channel coding scheme. Turbo code has a powerful low-SNR performance, superior anti-fading, anti-jamming ability to make it a number of communication standard coding scheme. The use of Turbo codes in 3G and 4G communication technology has proved its irreplaceable value. For deep space communication, channel coding also need to overcome the transmission distance, harsh transmission environment and so on. CCSDS (Consultative Committee for Space Data System) finally selected Turbo code as satellite communication and deep space communication channel coding standard.Turbo codes decoding structure is complex, FPGA implementation requires not only a large number of processing units, but also a large number of storage units to save the intermediate data. For the communication system receiver, the storage resources are extremely valuable, a large number of processing modules need to store buffer information and intermediate data, which for the FPGA itself, the storage resources are often unbearable. In this paper, a low-memory Turbo decoder based on FPGA is realized by adjusting the decoder decoding flow, reducing the intermediate data cache, and integrating the data storage format.This paper first introduces the CCSDS standard Turbo code encoder structure, and then derives the BCJR decoding algorithm, analyzing and simulating the different decoding methods on the decoding performance,and finally introduced the decoder algorithm and decoding process design and implementation. Based on the analysis and comparison of the decoding algorithm, the paper chooses the max_log_map decoding algorithm based on scale.A normalization scheme based on modular arithmetic is adopted in the algorithm implementation.Aiming at the design principle of low memory, a parallel decoding architecture of windowing design is designed, and a new decoding process and interleaving scheme are proposed. According to the characteristics of the decoding algorithm, an improved external information storage format is designed. Finally, the FPGA implementation of the decoder is introduced,the architecture and implementation details of different decoding modules are introduced.The decoder based on CCSDS-Turbo in this paper can save more than 25% of the total memory and 50% or more in some applications,which significantly reduces the storage capacity. in addition to achieving complexity with the traditional decoder is basically the same.The decoder implemented in this paper has been fully tested in indoor and outdoor environments. The test results show that the performance of the decoder is not affected and the performance index meets the design requirements.