Design And Simulation Of Novel Multi-gate Junctionless MOSFETs

In the development of CMOS, the size of the device is decreasing. Junctionless device has been proposed to improve the characteristics of CMOS device. Junctionless device has the same doping level on the source/drain and channel which makes this device easy to process.Junctionless device also has lower short channel effects. Otherwise, multi-gate SOI device is used widely. The double-gate, tri-gate and gate-all-around(GAA) devices show the excellent performance. However, when the gate length of the junctionless device is reduced to 20 nm,the characteristics of the conventional JL are not satisfied especially on subthreshold slope(SS)and drain-induced barrier lowering(DIBL). Therefore, it is urgent to improve the structure of traditional junetionless device.The main work of this paper is to improve the structure of the traditional junctionless devices, which can improve the electrical properties, reliability and radiation characteristics by changing the structure of traditional JL. We have designed three kinds of junctionless devices to improve the performance of the traditional junctionless devices. Firstly, we design an asymmetric double-gate junctionless device. Through the transformation of the gate, the structure of symmetry double gate for traditional double gate device is changed to asymmetric double gate. Through the simulation of TCAD Sentaurus software, we found that the new device has a better performance than the traditional junctionless device including the basic electrical characteristics and reliability. Secondly, we design a novel P+ sidewall tri-gate nanowire junctionless device. This new device is proposed by using P+ type silicon as the sidewall to achieve lower leakage current. By the simulations, we find that this new device has a better OFF current than the conventional junctionless device. Otherwise, the subthreshold slope and DIBL for P+ sidewall JL can also be reduced than conventional JL when the gate length is 10 nm. Lastly, we design a novel non-uniform doped channel junctionless device. This new device has a lower doping level on the channel near the source(Nsc). For the simulations, we found that this new device can improve the single particle radiation capability of conventional junctionless device which can effectively improve the carrier discharge ability and reduce the generation of floating body effect. Through the design and simulations of these three kinds of new devices, we have improved the characteristics of the junctionless device. Therefore, these new devices can meet the challenge to CMOS devices.