Study Of The Novel 3D Field Effect Transistor Applied To Limit Nano-scale Integration

The main study objects of this article are U shaped channel field effect transistors of which the channel widths are zoomed out to 5nm to 6nm.The junctionless field effect transistor(JL FET)is chosen to be study in this passage because of its easier manufacturing process and less short channel effect in such a small size compared to FETs with PN junctions,of which the manufacture is complex and the doping process is too hard to achieve in sub-ten nanoscale sizes.Comparison between the classical simulation and the quantum simulation is made to ensure more précised simulating results of the performance of the devices in case that the macro classical theory is no longer suitable for devices in such a small channel width.The main contents of this research are the quantum simulating verification of the proposed H gate JL FET(HGUC JL FET)and the stability of the HGUC JL FET under different temperatures,modeling the newly proposed high integration and high performance devices U shaped channel square gate JL FET(UCSG JL FET)and U shaped channel auxiliary square gate JL FET(UCASG JL FET)and optimizing their structures.Simulations with the same classical simulation optimized structure of the device HGUC JL FET is completed with both quantum models and classical models,and some parameters that have not been optimized completely under classical simulations are optimized again with quantum simulations to reach its best electrical characteristics.The stability of the performance of the HGUC JL FET in which the temperature is growing up is also studied.Parameters that might influence the performance of the UCSG JL FET and UCASG JL FET are optimized after modeling the two device structures,making the devices better electrical characteristics in such high integrations compared to traditional field effect transistors.The output characteristics of the two newly proposed structures are simulated for verifications and the temperature characteristic test is made after the final optimization.The semiconductor simulation tool Silvaco TCAD is introduced to finish all study contents in this research,of which the tool Devedit3 D is used to edit the device structures,the tool Deckbuild is used to simulate the device with related models,methods and voltages,and the tools Tonyplot and Tonyplot3 D are used to display the results of simulations.All the parameters that might influence the performance of the devices are optimized by being simulated in different values.All the simulations in this passage are operated under quantum models after the comparison being made between classical simulations and quantum simulations to obtain more précised simulating results.