The Study Of Novel Junctionless Field Effect Transistor

With the developing of semiconductor technology,the metal oxide semiconductor field effect transistors as the main units of large scale integrated circuit,become shorter and shorter,in the other word,the distance between the PN junctions in MOSFET reduced gradually which have reached tens of nanometers or even a few nanometers.The main purpose of the device size shrink is to promote the integration of integrated circuit,but there is also a great challenge waiting for us to solve is that it will brings some negative effects which hard to avoid.First of all,because of the atomic diffusion and natural distribution,to produced a semiconductor junction in a few nanometers or tens of nanometers distance is real difficult,the thermal budget and annealing technology is almost difficult to achieve;secondly,a reduction of channel length will bring severe short channel effects which will seriously affect the performance of devices.In order to solve a series of difficult problems which appeared in the nano scale MOSFET,Some novel type semiconductor devices have been proposed which called I Gate JL FET and U channel JL FET.The basic model of the proposed I Gate JL FET and U channel JL FET are the simple JL FET which had also been called a gate controlled resistor.In the case of the device size continues to decrease,the JL FET can effectively suppress the short channel effects,and it have no any junctions in body,which avoids the difficulty of manufacturing process.I shaped JL FET is the optimization of gate optimization for the conventional JL FET,and it has more superior performance than the conventional JL FET.U channel JL FET is a new type of structure which has been developed after extensive research on the general JL FET.In the structure,U channel JL FET have two additional vertical channel compared to the normal planar JL FET,so the advantage of this structure is,in the same area of the chip,the effective channel length of the U channel JL FET will become larger than the normal one which can effectively reduce the degree of sensitivity to the SCEs.And the GIDL(GISL)current can be reduced effectively by adjusting the height of extended region.In this paper,the SILVACO TCAD simulation software will be used for all the simulation of the novel JL FET.By adjust the design parameters,the characteristics of I Gate JL FET and U channel JL FET is further improved,and the different effects caused by the change of various parameters will be well known by data analysis,then the principle and basic electrical characteristics will be explained in detail,finally,the most optimal parameters of I Gate JL FET and U channel JL FET will be obtained and related theoretical basis will be established for the development of such transistors.