Research And Design Of SOI High Voltage Devices For Total Dose Radiation Hardness

Compared with conventional bulk silicon devices,SOI devices are characterized with smaller parasitic capacitance,lower power comsumption and anti-latchup effect.Due to the dielectric isolation between devices and substrate,SOI devices exhibit good resistance against single event effect and dose rate effect.However,limited to long drift distance,thick field oxide and buried oxide,high voltage SOI devices are susceptible to total ionizing dose effect.To ensure long-term and reliable working conditions of devices in radiation environment,effective radiation hardness by design is quite meaningful.This thesis mainly works on the radiation hardness against total ionizing dose(TID)effect for 300V silicon-on-insulator(SOI)lateral double-diffused metal-oxide-semiconductor field effect transistor(LDMOS),and structure with ultra-thin shielding layer is proposed.Secondly,radiation hardness for 120V SOI LDMOS is studied.Structure with thin and partial field oxide is proposed.Thirdly,this thesis studies on layout hardness of SOI complementary metal-oxide-semiconductor field effect transistors(CMOS).Enclosed-gate structures were taped out for fresh measurements.Considering the TID hardness of 300V SOI LDMOS,this thesis proposes a structure with ultra-thin shielding layer.This paper simulates impact of introduced holes in the transistor oxides under harsh environment based on device and process simulation software,with optimized layer length,implantation energy,lateral distance and dose window,and achieves the goal of linear current hardness(linear current increment decreasing from 447%in conventional structure to less than 10%in proposed structure)while maintaining pre-rad and post-rad breakdown voltages above 300V under total dose of 0-500krad(Si).For radiation hardness of 120V SOI LDMOS,this thesis designs normal oxide and N₂O oxide,which both differ in field oxide lengths.Through post-rad measurements and simulation calibration,trapped oxide charges inside oxides are extracted,and impact of oxide length and process on radiation hardness is verified.Considering the TID hardness of 20V SOI CMOS,this thesis studies on radiation response of conventional non-hardened symmetric and asymmetric layouts,reveals the mechanism of leakage current,and designs hardened layouts.Layouts with bar-type gate and enclosed gate were both designed,and the latter one was taped out and tested.On the other hand,to realize compatibility with TTL level,the same design was applied for 5V SOI CMOS.Enclosed-gate and hardened bar-type gate structures were taped out for fresh measurements.