Research On New Layout Sensitivity Model And Extract Algorithm

In the semiconductor industry,the yield of production,generated by integrated circuit(IC),is always the direction of the industry to make great efforts to improve itself,and the promotion of it can reduce the production costs,increase the profits,and save the resource.With the drastic development of the manufacturing technology of IC,the expansion of scale,and the gradually decrease of the feature size,the loss of the yield of production creating by the manufacturing defect is getting serious.At present,In the process of the production of IC,the main reason of the decline of the yield of production is in the phase of network layout,and the layout route determines the yield of production.In the process of layout optimization,it is crucial that how to choose the network waiting to be optimized.Viewing the sensitivity as a mothed to estimate the yield of production and choose the network to be optimized,can solve the problems above perfectly,and achieve the goal of improving the yield of production of IC eventually.First,a visual matrix sensitivity(VMS)-based algorithm is proposed in this paper.The paper define a two-dimensional visual matrix,which is used to store the information of short circuit and open circuit produced by the different networks and a single network,respectively.On the basis of the sensitivity of the information calculation of the visual matrix,the traditional sensitivity calculation model and the visual matrix is combined in this paper.In addtion,VMS is a acceleration algorithm,the addition of VMS on the existing sensitivity calculation model can short the computation time of the traditional model.The experimental results show that the algorithm not only can maintain the calculation results of the traditional model,but also can reduce the calculation time,especially for the complex layout.The model of the weighted sensitivity(WS)and the WS on edge-based layout optimization algorithm are proposed in this paper.WS,a new model to calculate the sensitivily,can effectively reduce the impace of the defect of the appearance of the big probability on the yield of production of IC.WS use the method of mathematical morphology to calculate the critical area of the network,base the circuit area and the area of network to calculate the weighted sensitivity,and apply the VMS algorithm to improve the calculating speed of WS.The WS on edge-based layout optimization algorithm is one of the applications of WS,andit combines the model of WS and the graph theory in data structure to carry out the layout optimization.Using the characteristics of figure,the algorithm can obtain mutiple networks,to be optimized,during one traverse.WSOE gives full consideration to the connectedness between the networks when choosing the network,which is waiting to be optimized,to find a path which connects the multiple networks the most closely and has the most notable effect on the layout optimization,where the path contains multiple networks.