Study And Verification Of MMU In 32-bit PowerPC Processor

The dissertation derives from the Shenzhen State Microelectronics Ltd undertaked Nuclear high-based project: design a 32-bit superscalar,high-performance Power PC X Type microprocessor. CPU is the foundation of computer industry and the whole information industry, The Power PC processor due to its high performance, low power consumption and strong stability characteristics are widely used in network communications, aerospace, industrial control, national defense and security fields, Memory management unit is an important component unit of the processor So the research on Power PC processor is of great academic and realistic significance., using the memory management unit can solve a series of problems such as large loader, time division multiplexing, memory protection, memory sharing greatly improve the performance of the processor. The dissertation mainly focuses on the study and verification of X type microprocessor memory management unit.MMU is based on the idea of virtual memory, can adopt the memory paging technique(multilevel page table, reverse page table) and memory segmentation technique to divide the process and memory. In the address translation, MMU increases TLB to improve the speed of address translation, the hardware structure of TLB and the hit rate by using the replacement algorithm decision. The main function of the memory management unit is the address translation and memory protection.The 32 bit Power PC X type processor in this dissertation has two structures of the same memory management unit: data memory management unit processing data access, instruction memory management unit processing instruction access. Each of the memory management unit comprises four of the block address translation registers, 16 segment register and a 128 entry TLB. MMU support three address translation mechanism: Real address translation mecha nism directly use effective address as the physical address to physical memory access; block address translation is actually using the segmentation technology would be the size of a configurable process blocks mapped to a physical block and block the physical memory of equal size of process block; segment page address translation is a combination of segmentation and paging technology, process page discrete mapping to physical memory by Segment page address translation. Memory management unit with the exception handling mechanismin the block address translation and segment page address translation the unit of memory protection as block or page.Memory management unit studied in this dissertation use reverse page table, compare with the traditional page table is greatly reduced in physical storage space occupied and in the page table migration greatly reduces the page migration replication overhead. The memory management unit use the main and side hash function sorted page table entries in the reverse page table to construct hash page table. Using open address method to solve the conflict in the hash page table, most can guarantee 16 processes running in the system, which makes the X processor is more suitable for the multi task processing, has the stronger performance compared with the traditional page table structure of the processor.After the detailed analysis of the 32 bit Power PC processor memory management unit, do separate module and system level verification of MMU. According to the functional characteristics of the memory management unit extraction test function point control set, and built a strong reusability, high efficiency of the verification platform. Verify the block address conversion on the memory management unit, section page address translation, address protection mechanism, structure and function of TLB, TLB replacement algorithm. The results of verification show that the MMU can be very good to complete the address translation, address protection function; structure and function of TLB, by the TLB replacement algorithm to meet the design requi rements.