Research And Implementation Of JPEG Compression And Stream Transmission Technology Based On Xilinx Zynq

In recent years,with the popularity of intelligent electronic equipment,a variety of specified hardware is becoming stronger and stronger.This kind of specificity can greatly reduce the cost of production and development.But in the experiment and study,what we need more is a reconfigurable hardware.In the reconfigurable hardware,we just need to do some simple software and hardware development to meet the demand of system design.In order to develop a complete set of JPEG compression coding equipment,this paper put forward a SOC solution based on Xilinx Zynq-7000 series which integrates ARM with FPGA.In the SOC,we design a handling solution regarding ARM as the main body in the compression coding and FPGA as the support with big data processing.In this paper we used the collaborative design method on the solution of hardware and software.On the hardware,the design and use of the interface is the key point of research.In traditional FPGA development,we usually need to do a lot of programming work to drive system interface.The new type of SOC is based on GUI design patterns.In this kind of design method,we do the whole hardware interface through the UI design that reduces the need for complex coding.On the software,the operation platform is ARM using standard C language for development.On the part of image compression,this paper studies and implements the JPEG compression algorithm and emphatically discusses the JPEG compression of DCT transform algorithm and quantitative algorithm.On the ARM side,this paper completes the optimization design of the algorithm.Then we complete the design of the frame structure and the design of the cache.The design of the frame structure is embodied in two parts,the input/output frame of JPEG encoder and the received frame of system instructions.The cache design is embodied in using the second level cache strategy on the input/output frame of encoder.We complete the stream transmission of data through the co-design of software and hardware.Finally the paper describes optimizations of the system.The optimizations mainly include the optimization of the code itself,the compiler optimization options and the hardware optimization.In these optimizations,the most important parts are the ARM Cache optimization,which is platform unique,and the optimization based on the set of the latest Neon instruction.These two kinds of optimization improve the operational efficiency of the system 7 times and 1.5 times respectively.Through the optimizations of software and hardware design,the whole system runs at the state of less resource cost and stronger performance.