Design And Realization Of The Embedded Video Compression Hardware Platform Based On DSP

In some cases that digital video supervisor are used, people hope video code can be transported into PSTN or GPRS wireless network. In this case the more efficient low-bit video compress arithmetic is in need.This paper designs and realizes a low-bit video compression hardware platform based on DSP. Firstly, on the basis of analyzing the output signals of the video ADC SAA7111, paper designs a ping-pang cache to collect and cache the image data, which make sure the image data frames can be cached entirely. Paper realizes the ping-pang cache operation logic by applying VHDL program, and does some function simulations. The result of function simulation reveals that this ping-pang cache can well cache the image data frame. Then paper emphasizes the DSP hardware design, particularly introduces some hardware design thought, such as how to design the DSP's least system, how to connect with external memory include SDRAM and FLASH, and how to design other on-chip peripherals. What follows is the discussion of several issues of high speed DSP PCB design. In the end, paper gives briefly introduction of the function and character of DSP's integrated develop environment CCS2.0, as well as some programming method.