Research And Design Of Topology In 4G/4.5G Communication Instrument Platform

With continuous evolution of LTE/LTE-A systems the requirements to the hardware platform is increasing. Improving the speed of digital processing chips is a solution to improve the performance of the system.But the gap between chip performance and system bus speed is widening.The communication speed among different components is gradually becoming the bottleneck of the embedded system.Based on the research and analysis of Serial Rapid I/O protocol and embedded systems, this thesis designs a complex structure of instrument platform. Then finished the program and the code, at last verified the program with the test cases. This thesis has completed the research and design of the complex topology on the 4G/4.5G communication instrument platform.First, the thesis describes the technical background and the significance of the selection of the thesis, and then introduces the function and principle of LTE-A terminal testing instrument architecture and protocol software design.Second, the thesis introduces the procedures of completing the driver module and system debugging. And then uses multi-cell carrier aggregation test case to make sure that the project could serve for the 4/4.5G terminal test instruments.Finally, the thesis summarizes the implementation procedures and describes the prospects of the terminal test instrument.