Research And Implementation Of External DSP Interface On Baseband Processing Board In GMR-1 3G Terminal Test System

With the development of satellite communication technology,the satellite communication has been widely used in the fields of international communication,radio and television,military communication,and mobile communication.The GMR-1 3G terminal tester is to test whether the radio frequency of mobile terminal conforms to the terminal radio frequency conformity specification instrument.The instrument for the development of satellite mobile communication system has a positive role in promoting.The thesis is taken from the development of DSP on the baseband board of the "GMR-1 3G Terminal Tester".This thesis is forced on the research and implementation of the interface between the DSP and the terminal,including the Ethernet interface between the DSP and the host,the SRIO interface between the two DSPs,the AIF interface between the DSP and the FPGA,and the DSP bootlaoder based on the IIC and EMAC interfaces.The research of each interface has covered demand analysis,scheme design,module introduction,concrete realization and result verification.In the DSP bootloader,this thesis has researched the DSP bootloader based on the IIC EEPROM and EMAC,and also has designed a new set of bootlaoder.The biggest difficulty of this design is multi-core,multi-DSP bootloader.In the implementation of DSP Ethernet port,the characteristics of NDK and socket based on the streaming protocol have been studied.A store and forward plan based on data frames in the receiver of DSP and the plan of concurrent transmission scheme in the sender of DSP have been designed to ensure that two multi-core DSP can communicate with the master.In the implementation of DSP between the SRIO interfaces,the thesis has studied the interruption mechanism between DSPs and inner DSP,and also has desiged the synchronization scheme of arbitrary between DSP and multi-thread concurrent transmission scheme.The key technology is the communication between any two threads on two DSPs.And the thesis abstract summary of the design pattern,so that it can be used in multi-chip multi-core DSP to achieve any two threads of synchronization.Based on the demand of AIF interface between DSP and FPGA,a multi-channel multiplexing,air-port alignment scheme and two schemes for transmitting different data streams have been designed,so that the AIF interface can transmit continuous data stream and burst data stream.By comparing the air gap alignment scheme with the existing scheme,the air gap alignment scheme has the advantages of satisfying the multi-channel air port alignment at the same time.The satellite terminal tester is an important part of the satellite mobile communication system.The DSP on the baseband is not only the interactive tool between the various modules,but also is the key of the physical layer algorithm processor.Research and implementation of the interface between DSP and other modules is the basis of the upper application,what‘s more,the quality of the interface has an great impact on the performance of the terminal tester.Therefore,the study of this content has a great significance.