Design And Implemention Of SPARC V8 CPU Simulator In Virtualized Verification System For General Embeded Software

With the degree of informatization getting higher in embedded systems, the functions of software are increasingly powerful and therefore the software architecture is designed more complex. In order to ensure the safety of whole system, people is prompted to pay more attention on improving the reliability of embedded software. The virtualized verification system for general embeded software developed by our laboratory aims at the highly customizable embeded system. Unlike the traditional testing hardware environment, this all-digital simulating platform is universal, flexible and cheap, it is satisfied for various kinds of testing requirements.The aim of this p aper is to design and develop a simulator with high effic iency and flexibilit y for the SPARC processor which is widely used in present domestic aerospace industry based on the virtualized verification system. Firstly, the features of SPARC instruction set architecture is studied and the simulation of it’s register file, execution of instruction and handling of trap is implemented wtih C programing languge respective ly. The interpretive execution technique is used to achieve high flexibility and support ric h debuging functions. The decoding cache technique is added to avoid redundant decoding and markedly enhance s the speed of the simulator. What’s more, the advantages of modern multi-core computer system is utilized fully by mult ithreading design. The Peterson algorithm is realized to protect critical section between threads effectively and for fear of the performance reduction caused by schedule between different processor cores, the major thread is binded to assigned core. Further, the high performance general graphics processor is explored to gain more performance improvement and the pre-decoding function is eventually realized with C UDA and obtain considerable speedup. At the end of this paper, the SPARC simulator is tested by both function and performanc e and the result shows that it gives consideration to both efficiency and flexibility and has strong practicability.This paper discusses several techniques to imp lement a effic ient and flexible SPARC simulator and proves that it is pratical and better to displace traditional testing hardware environment with simulating platform. The outcome enrichs the kinds of processor architecture supported by the virtualized verification system and offers valuable references for future study.