Design Of A Low-Resistance DMOS With Slotted Charge Balance Structure

Low-voltage power TRENCH MOSFET has been widely used in computers,telecommunications, automotive applications and other industries due to its well-known intrinsic advantages: high input impedance, low drive power, short switching time,thermal stability, etc. However, in recent years, 4C industry's rapid development requires products to have high performance and develop in the direction of the microminiaturization. Miniaturization requires power MOSFET having smaller on-resistance while high frequency requires low switching losses and this is closely related to the gate charge of the device. If device's on-resistance and gate charge can be reduced simultaneously, the chip size can be further reduced and the working frequency of the device can be improved. In order to meet the needs of the current market, this paper proposes a new power DMOS structure for low voltage applications based on the traditional TRENCH MOSFET. This new structure is named as BFP-TDMOS and is a low resistance DMOS with slotted charge balance structure. An exemplary process for fabricating the new MOSFET is designed and the cell and terminal are simulated based on the process.In this thesis, the development of power DMOS is firstly introduced. Then TRENCH DMOS's working principle of, electrical parameters and the commonly used terminal structure are described in detail. On the basis of a thorough understanding of the on-state resistance and gate charge of TRENCH DMOS, a low resistance DMOS with slotted charge balance structure is proposed and is as BFP-TDMOS. With the introduction of field plate and the N-type lightly doped region, the structure's specific on-resistance is expected to be reduced. Then, a 40V N channel BFP-TDMOS is designed and is compared with a 40 V SPLIT-GATE DMOS. According to the comparison, BFP-TDMOS is superior to SPLIT-GATE DMOS in terms of specific on-resistance, gate-source capacitance and reverse recovery characteristics. The results meet the expectations. Based on the TRENCH DMOS process platform, an exemplary process for fabricating BFP-TDMOS is designed. The key process parameters of the device cell are simulated by the process simulation software TSUPREM4, and the optimal cell parameters are determined on the basis of satisfying the design requirements. In addition, the deep trench terminal structure is adopted, and the terminal structure is designed and optimized. After the final simulation, cell's breakdown voltage reaches 44.2V, specific on-resistance is 1.81 × 10-4?·cm-2, threshold voltage is 2.2V,gate source capacitance is 4.19 × 10pF/cm2, gate drain capacitance is 8.25 X 106pF/cm2,and terminal's breakdown voltage is 47V. All these results meet the design requirements.Through the structural innovation, the low resistance DMOS with slotted charge balance structure proposed in this paper reduces its specific on-resistance. This structure is in line with the current development trend of low-voltage power DMOS and has some reference value for low FOM power MOSFETs for communication applications.