Design And Implementation Of An IP Protection Approach With High Efficiency And High Security

With the rapid development of semiconductor technology,the integration and complexity of the large scale integrated circuit system is higher and higher,and design is becoming more and more difficult.Developing such systems from scratch has become an insurmountable task for most developers.A system-level design approach reusing custom and third-party intellectual property(IP)modules has become a standard procedure.With its reprogrammability,low design cost and excellent capacity,field programmable gate array(FPGA)has become a popular design platform.As FPGAs have been adopted in many electronic system designs,IP protection of FPGA implementations has become one of the major concerns of the designers.This thesis proposes a novel RO PUF-based FPGA IP protection mechanism which embeds PUF logic in the IP core designs in order to efficiently protect IPs from being cloned and illegal usage.Integrating RO PUF into FPGA implementations for practical applications still faces major challenges,including 1)it always introduces considerable hardware overheads;and 2)the limited set of challenge-response pairs(CRPs)due to limited circuit resources may not authenticate a large population of FPGA IP cores with less error.To address these issues,this thesis firstly proposes an effective technique,logic fusion.It combines the RO logic of the PUF with the normal circuit logic,without increasing logic resource usage in FPGA.Secondly,a post-processing procedure is exploited to expand the set of CRPs from the designed RO PUF.Experimental results show that the reliability,randomness and uniqueness metrics of the designed RO PUF are 99.97%,50.37% and 49.83%,respectively.Compared with the existing RO PUF design techniques,the area overhead can be reduced by 45% with the same performance.