Research And Design Of FPGA-based Low-overhead RO PUF

For the advantages of high speed data processing,low power consumption and reprogrammable,Field Programmable Gate Array(FPGA)has been widely used in automotive electronics,consumer products,medical devices and other fields.With the popular applications of FPGA,hardware security and information security problems about FPGA are more and more prominent,such as unauthorized use of intellectual property(IP)cores,security storage of keys and hardware trojans etc.Through generating unique and random sequence by utilizing the internal manufacturingvariances of each chip,physical unclonable function(PUF)can provide an effective support to address above-mentioned hardware security problems.A kind of FPGA-based ring oscillator(RO)with low hardware overhead has been designed in this paper.Xilinx 6 series FPGAs have six-input-dual-output LUT,which is composed of two five-input-single-output LUTs and one MUX.Through implementing function of MUX and inverter in each five-input-single-output LUT and cascade LUTs,two ROs in the same CLB can be formed.ROs should be configured by the controlled ports to form two separate and effective ring channels.And then we enable two adjacent ROs in turn.The responses of RO PUFs can be obtained by computing the frequency difference.We have done experiments about the responses of 16 RO PUFs on the Xilinx Spartan-6 series FPGA development board and analyzed the response data of 16 this kind of RO PUFs.The experiment results demonstrate that our design of FPGA-based low-overhead RO PUF is practicable and has the feature of low hardware overhead with strong randomness and good uniqueness.