Research On The Key Technology Of Physical Unclonable Function On FPGAs

In recent years,the development of intelligent hardware based smart terminals and interactive devices has a large-scale popularization,and make the entire information system more intelligent and convenient.However,the diversity and complexity of application environment will make the entire information system risk resistance be fragile.As an important hardware security primitive,Physical unclonable function(PUF)which exploits intrinsic process variation,generates unique identification signature.The properties of lightweight and unique tamper-resistant endow PUF with great advantage in the protection of intellectual property rights,the Internet of things system security and hardware certification.As field-programmable gate array(FPGA)application has flexible configuration circuits features,its self-security and reliability issues have gained lots of attention over the recent years.PUF technology can protect circuit configuration from the hardware level with less overhead.Based on the implementations,characteristics and application fields of FPGA PUF,this paper systematically analyzes two kinds of model and the circuit structure of storage and delay based FPGA PUF,and points out that the existing FPGA design excessively pursues randomness of response and ignores the overall hardware cost and flexibility.Three key technologies in the design of FPGA PUF including the random characteristics of manufacturing process,reconfigurable PUF circuit technology and multi-node key matching are studied to improve hardware resource utilization,circuit constructure flexibility and stability.The contributions of this work can be summarized as follows:A type of high efficiency glitches PUF circuit design is introduced.After analyzing the low hardware resource utilization and lack of compatibility problems in glitch PUF design,this high efficiency structure design was motivated by the glitch PUF design architecture which uses the delay characteristics of multiplexer and switch matrix.The switching latency of the multiplexer can be adjusted to ensure that the 'glitch' signal has PUF characteristics by changing the input state of multiplexer and the distribution of the switching matrix.Compared to the large resource consumption of arbiter PUF and ring oscillator PUF,this design increases a single CLB output to two bits and makes Slice resources utilization up to 100%.A more flexible crossover RO PUF design is proposed.Previous RO PUFs improve flexibility and reliability through adding redundant ROs.A crossover RO PUF design is proposed to improve flexibility and reduce hardware overheads.The basic idea is to implement one-to-one input-output mapping with Lookup Table(LUT)-based interstage crossing structure in each level of inverters.This structure can not only achieve the goal of dynamic configuration path,but also solve the problem of output signal randomness when different configuration has great influence on signal transmission delay.In addition,individual customization on configuration bits of interstage crossing structure and different RO selections by challenges bring high flexibility.A shared key authentication encryption algorithm based on FPGA PUF is also proposed.Aiming at the weakness of hardware resource consumption and one-to-many authentication in IoT authentication algorithm,the design of one-to-many mode authentication algorithm based on PUF is studied.By adjusting selection input and challenge input signal in two different configurations,the cross reconfigurable RO PUF can output the same response.The basic framework of authentication and data communication protocol based on shared key is also designed,and further expands in terms of timeliness and energy consumption.Experiments show that the proposed authentication encryption algorithm has lower hardware overheads in FPGA with high reliability,and has great advantage in one-to-many authentication mode.