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Research On UVM-based I~2S Verification IP

Posted on:2018-04-29Degree:MasterType:Thesis
Country:ChinaCandidate:L YuanFull Text:PDF
GTID:2348330512979918Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of integrated circuits, the technology of SoC design is now more and more mature. IP development and reuse have become the primary strategy to achieve high efficiency design of SoC, and puts forward higher requirements for veri-fication. As a very important section of IC design, verification go through the entire chip design process. The task of verification is primarily responsible for constructing a verifi-cation environment based on chip specifications and performing verification and regres-sion under this verification environment. To reduce the verification time and improve the efficiency of verification, it needs to realize the reusability of the IP verification environ-ment. Verification IP is a verification model that can self-generate stimulus and automate data comparisons. In addition, the verification IP can be ported between different projects.An I~2S verification IP is designed by using UVM, the current mainstream verifica-tion methodology. The main work is as follows:1. Thoroughly study the UVM and I~2S bus specification, and develop an I~2S verifi-cation IP based on UVM. The verification IP mainly includes the environment, transmitter agent, receiver agent, sequencer, driver, monitor and protocol modules and other compo-nents. The transmitter agent and receiver agent are responsible for sending and receiving data according to the I~2S protocol specification.2. Sequences and test cases are designed according to the requirements of I~2S veri-fication IP. Test cases can be divided into four types: I~2S format test, left-justified format test, right-justified format test and pcm format test. They are used to test whether the transmission of verification IP is correct in the I~2S format, left-justified format, right-justified format and pcm format. Finally, the results show that the verification IP can op-erate normally in various data transmission formats.3. The function points are analyzed and the functional coverage model is developed according to the I~2S bus specification. The functional coverage model consists of three coverage groups: coverage group of channel status, coverage group of channel length,and coverage group of configuration. Finally, complete the functional test of I~2S verifica-tion IP are performed driven by functional coverage, and the results show that this verifi-cation IP can simulate the data communication of I~2S bus correctly, with 100% of the ration of function coverages.
Keywords/Search Tags:UVM, I~2S, Verification IP, Coverage
PDF Full Text Request
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