Design Of A High-Performance Continuous-time ?-? ADC

Over the last few years,the wireless communication technology has developed considerably.In all types of receiver systems,the analog-to-digital converter(ADC)acts as bridges between analog and digital parts,and plays a very important role in the overall system.Due to the advantages of hign bandwidth,low power consumption and high accuracy,the continuous-time ?-? ADC is widely used in wireless communication systems,so it has received extensive attention and research.In this paper,a continuous-time ?-? ADC with 30MHz bandwidth and 13bits precision is designed based on the TSMC 65nm process for a Zero-IF receiver.In this paper,the implementation of ?-? ADC with continuous-time is selected by comparing the implementation principles and advantages and disadvantages of different ADCs.When designing the continuous-time ?-? ADC in this thesis,the stability and power dissipation of the system is considered and validated by matlab modeling.Finally,a 20-times oversamplingthird-order four-bit single-loop feedback structure is choosed.In the circuit analysis,the influence of the limited bandwidth and finite gain of the integral amplifier on the system is fully demonstrated,and the change of the integrator coefficient is corrected by the capacitor array.For facilitating the following circuit design,this thesis builds a system model using veriloga and ideal devices in cadence.By substituting the indicators of each sub-module into the system model for iterative simulation and verification,the parameters of sub-module are finally determined.The loop delay is corrected by adding additional delay compensated DAC while the effects of clock jitter is reduced by usinge multi-bit quantizer and DACs.To improve the linearity of multi-bit DAC and reduce the influence of DAC nonlinearity on the overall performance of the system,a first-order DWA algorithm is adopted.Finally,the signal-to-noise ratio of the continuous-time ?-? ADC can reach 82dB for the ± 600m V swing,1MHz-30MHz bandwidth input signal at 1.2G sampling frequency.And the corresponding layout design is also completed meeting the system design requirements.