The Design Of A Continuous Time Bandpass ?? Modulator In RF Receivers

With the development of electronic and communication technology, the demand of radio frequency receiver systems has been increasing continuously. As the bridge between analog and digital, analog-to-digital-converters (ADC) influence the property of receivers. An ADC with good performance can even simplify the stucture of the receiver. The continuous time band-pass ?? ADC can achieve high dynamic range because of the band-pass noise-shaping and filtering character, it is becoming the hot spot of study in recently.Firstly, the latest development of continuous time band-pass AS ADC at home and abroad is studied in this thesis. After then, the basic principle of the ?? modulator is introduced. The difference between discrete-time and continuous-time modulators and the conversion methods from discrete time to continuous time is summarized. And also the complex ?? ADC structure by using complex filter is introduced. The structure with fifth-order modulation and 1.5-bit quantization is determined. This thesis adopts the feed-forward structure, which balances well between power consumption and design complexity. At the same time, the design adjusts the positions of the zeros. Using the method of invariant-impulse-response(IIR), the structural parameters in discrete time are converted into continuous time domain. After the system simulation, the circuits are designed. Because of the higher requirement for the former integrators, a RC integrator is applied for the first integrator. And Gm-C integrators are usd for the later integrators. A folded cascade amplifer is used in the first integrator, and the input transistors are biased at sub-threshold region to reduce the intermodulation product. The Gm cells are biased by master-slave structure in order to increase the linearity. The 1.5 bits quantizer is implemented with low reference voltage to scale down the feed-forward coefficients, and the power is reduced. A current steering DAC is used as the feedback DAC. To improve the mismatch of the current units, randomization is used.The circuits and layouts were designed in SMIC 0.18um CMOS technology. The power supply was 1.8V and the sampling rate was 26 MHz.Inputing signals centerd at 700 KHz with 812.5 KHz bandwidth. The chip test showed 59.2dB SNR,64.8dB SFDR and 63dB DR with 4.35dB full scale input signal. The power comsumption of the two paths modulator was about 2.3mW.