The Implementation And Verification Of Square Root Unit Based On SRT4 Algorithm

Square root is one of the basic operations defined by IEEE 754 floating-point standard.Now,it is widely used in several fields such as digital graphic processing and numerical analysis and so on.A better algorithm is vital to improve the performance of CPU.A simple and widely implementation of square algorithm is digit recurrence.The SRT algorithm proposed by Sweeney,Robertson and Tocher(SRT for short)is the most common implementation of digit recurrence square in modern microprocessor whose advantages are less delay and less area costing.The main works are to study the SRT algorithm on which the designed square root unit is based.Finally,the verification and synthesis of that that unit is done.The detail is as follows:a.the theory of this algorithm is delivered including the choice of the radix and obtainment of selection constants mk and the generation of F.What's more,at the end of iteration,the On-The-Fly conversion of redundant into conventional representations of the root is called for the purpose of reducing delays.b.Basing on above theories,a square root unit of radix 4 is designed with Verilog HDL.That unit contains several adder,election logical module,result saving module and a module generating F and so on.It takes about 30 clock periods to complete once extract calculation.c.In the last paragraph,verification of designed square root unit was done with NC-Verilog provided by Cadence Corporation whose outputs show that the unit is correctly designed;synthesis is completed as well to obtain the parameters of this design including area,power consumption,path delays and so on.After optimization,the delay of this unit can be 300ps and the power 8.0897mW,meanwhile,the area is 13273.7?m2 which meet our expectation.d.The fore-end design procedure of digital IC is discussed.A better comprehension of using HDL and corresponding softwares is gained.