Research On MPSoC High-reliability Communication System Based On Cross-layer Design

With the increase of the integration and the reduction of feature size of single chips,the number of cores integrated on a single chip has increased rapidly.On-chip network,because of its good scalability and high communication bandwidth,has become the currently most popular inter-core interconnection scheme of Multi-Core System-on-Chip.However,with the continuous reduction of the chip feature size,the fault rate of the on-chip network also increases by crosstalk,coupling,Single-Event-Upset and so on.Therefore,the fault-tolerant design of the on-chip network has become an important research hotspot in recent years.As the fault-tolerant design will inevitably introduce a variety of overhead,how to balance the reliability and cost has become the focus of inter-core communication mechanism research.In this thesis,the transient faults on the on-chip network link are studied,and a high-reliability inter-core communication mechanism based on cross-layer design is proposed.The mechanism not only can effectively enhance the reliability of inter-core communication,and will not introduce too much area and power consumption.Firstly,this thesis studies the classification,sources and modeling of faults in the on-chip network,and points out that there are some problems in proposed transmission schemes,such as high overhead.To overcome these problems,this thesis implies a more reasonable and more intuitive bit-fault-model to represent the link fault of the on-chip network,and design the fault-tolerant transmission scheme design based on the model.Then,aiming at the reachability of packet,this thesis proposes a high-reliability error detection method based on cross-layer design,which is used to protect the key routing information in head flits.The fault-tolerant design is mainly composed of the lightweight fault detection modules in the routers,the error correction modules in network interface and the related control logics.In this design,head flits perform hop-to-hop error detection at the data link layer,and then reuses the error bits by decoding units in network interfaces to perform end-to-end error correction at the transport layer.By this scheme,head flits can get a higher degree of reliability to ensure that the packets can reach the correct destination.Moreover,considering the data reachability,this thesis proposes a low reliability and reliable fault-tolerant design for payload,and introduces a shorten Hamming(72,64)code to end-to-end error correction.The code is capable of correcting 1-bit random errors and detecting 2-bit errors to ensure the reliability of the payloads.At the end of this thesis,the ESYNET software simulation platform and Synopsys EDA tool are used to evaluate the proposed fault-tolerant design.The packet delivery rate,average packet latency,power consumption and area overhead are analyzed and evaluated comparing with some other transmission mechanisms.It can conclude from the experimental results that the proposed transmission scheme in this thesis does not introduce too much overhead,while ensuring the high reliability of the inter-core communication,and achieves a good balance between the performance and overhead of the on-chip network.