Font Size: a A A

Design Of NoC Fault-tolerant Route Based On Error Detection Retransmission

Posted on:2017-09-13Degree:MasterType:Thesis
Country:ChinaCandidate:G W HouFull Text:PDF
GTID:2348330509463143Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of IC fabrication techniques and the number of integrated cores in the current So C(System-on-Chip) increasing, the problem of poor scalability and bandwidth limitation on a single bus become much more obvious. To overcome the insufficient of the single bus, No C(Network-on-Chip) is proposed and developed. No C is a feasible scheme to solve a series of problems arising from growing number of So C communication components.It can improve the performance of So C effectively. However, data transmission in No C system may be subjected to fault due to various reasons, which will influence the communication quality of the No C system. As semiconductor process technology scaled, the majority of faults in No C are leaded to interferences. Thereinto, transient faults which are resulted in by interferences have been paid more and more attention. To improve the reliability of chips, effective fault-tolerant mechanism has become the key method to deal with the problems of transient faults in No C, which means fault tolerant algorithm of No C has become a new hot research topic.This paper researches fault-tolerant mechanism of No C. Based on the analysis of existing fault-tolerant algorithms on transient faults at home and abroad, the paper presented a modified hybrid error detection retransmission fault-tolerant mechanism by comparing the performance of traditional one. The characters of the new scheme are as following list: 1) According to the different weightbetween head flit and data flit, head flit uses a router-to-router(r2r) error detection retransmission algorithm while data flit using the end-to-end(e2e) one. In this way, the reliability of head flit transmission is ensured and, at the same time, the delays of data transmission won't increase obviously, which makes a remarkablebalance between reliability and delay;2) Comparator is used in the r2 r retransmission mechanism to instead of encoder/decoder. It will reduce the area of the chip. Three mode redundancy are used to improve the reliability of head transmission; 3) Timeout detection retransmission mechanism is designed to detect the phenomenon of packet loss and get a new retransmission packet, which solves the problem of packet loss.The hybrid error detection retransmission router is qualified by simulation verification, and several approaches are selected to compare with the new fault-tolerant route algorithm based on error detection retransmission. These approaches include route without fault tolerant, r2 r retransmission algorithm and e2 e retransmission mechanism. The results show that the throughput rateperformance of the new algorithm is 24% higher than the e2 emechanism based on error detection, and 18% higher than the e2 e algorithm based on error correction when some errors are introduced into the No C route. The fault-tolerant performance remains stable.The throughput rate performance is more distinguish when the error rate is higher. The results indicate that the hybrid error detection retransmission route is able to solve the problem of data transmission with 2 bits errors; if the errors are more than 2, it also can guarantee the reliability of data transmission by employing a strongencoding program. Furthermore, the modified hybrid error detection retransmission route can not only guarantee the reliability of the data transmission, but also get a great balance among delay, area and reliability.
Keywords/Search Tags:Network-on-Chip, Reliability, Fault-Tolerant, Hybrid Error Detection Retransmission
PDF Full Text Request
Related items