The Research Of Radiation-Hardened-By-Design High-Speed Clock And Data Recovery Circuit

Currently, the exponential growth of the amount of communication data makes the high-speed data communication system become a research focus in the field of communication; Used in aviation, aerospace and nuclear industry, electronic systems will face the harsh radiation environment, as the core part of the systems,integrated circuits must take radiation-hardened measures,so as to ensure the stability and the reliability of the electronic systems work under extreme conditions; High speed and high performance analog circuits /digital analog hybrid circuits are more sensitive to various types of radiation effects, and there is no general radiation hardened design(RHBD) technologies, which has become the focus of research on radiation-hardened integrated circuits. Clock and data recovery circuit(CDR) is one of the most important sub circuits in the receiver of high-speed serial communication system, and it is bottleneck of high speed serial communication system for higher transmission rate, it is also the study focus of high-speed serial communication system of radiation-hardened.Based on investigate and survey of CDR on the domestic and foreign at present, combined with the existing RHBD technologies and the circuit analysis, the circuit implementation and radiation-hardened methods of the phase interpolator(PI)based on CDR has been studied particularly, and a PI based on CDR is realized with 65 nm CMOS standard process.The paper mainly carried on the following research work:(1) First of all, the basic principle, main structure and performance of the CDR are analyzed in detail, through comparative analysis, the PI based on CDR is choosen for research;Then the basic principles and implementation methods of the PI is studied, and the scheme of converting the current signal to voltage single through the load resistance is choosen for PI achievement; Finally, the Z domain model of the PI based on CDR is analyzed, which lays a theoretical foundation for the subsequent circuit analysis and design.(2) The effects of single event transient(SET) effect on PI based on CDR are analyzed in detail. The PI based on CDR includes frequency tracking loop and phase tracking loop, the paper mainly put forward the RHBD technologies on phase tracking loop, especially on the phase interportator: including strengthening digital control circuit, within the range of allowable power dissipation increased tail current and reinforcement bias circuit.(3) A PI based on CDR is realized with 65 nm CMOS standard process. Irradiation simulation results show that: Pass through hardening digital circuit in PI, it can avoid errors of PI control words; pass through reasonable setting of the tail current source(as large as power dissipation allowed), it can restrain influence of PI by SET effect; pass through hardening the bias circuit of PI, it can decrease influence of PI by SET effect as soon as possible. The electrical properties simulation results show that: the highest data rate of CDR reaches to2.5Gbps, and jitter of recovery clock is lower than 65 ns, meets the design targets.