Font Size: a A A

Design And Implementation Of A Radiation-hardened PLL Based On130nm Bulk CMOS Process

Posted on:2014-03-23Degree:MasterType:Thesis
Country:ChinaCandidate:J J LvFull Text:PDF
GTID:2268330422973771Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of aerospace applications in our country, more andmore electrical systems need to work in radiation environment of outer space andnuclear explotion. High engery onizing particle from radiation environment penetratesthe sensitivity point of the electrical systems may lead to single-event effects (SEE).One type of effect resulting from SEE is single-event transient (SET). SET tends toaffect the PLL system more seriously with the shrinking of device feature sizes andsupply voltage and the increasing of operating frequencies. The phase-locked loop (PLL)affected by SET can result in clock signal degenerates, even lose lock which exertdisastrous consequence to the entire system. SET has been considered as the maincausation of the failure of spacecraft. Studies demonstrate that the SET has been themajor threat to PLL system.In this thesis the single ion sensitivity in the convertional PLL is investigated basedon the circuit-level simulation. Main study is focusd on the influence of SET to theCharge Pump (CP) and the voltage-controlled oscillator (VCO) and the radiation hardentechniques of them. A radiation-hardened PLL was designed and fabricated in a130nmCMOS technology. Radiation experiment demonstrates that the PLL work normallywith LET of91MeV cm2/mg without latch-up and losing lock, and the cycle to cyclejitter of the output signal in the radiation environment has little change with it in thenormal environment. Main work and innovation of this thesis is as follows:1. The paper studies the SET effects on CP and RHBD methodolog to reduce theSETsensitivity of the CP. Firstly, based on the systematic SET model of PLL, the SETis studied in time domain. The analysis from time domain indicate that the ion strikessensitivity of CP is related with loop parameters, and optimizing the loop parameter canimprove SET resistance. Then, a hardened CP is designed with the optimized loopparameter and it has an improvement in SET sensitivity.2. An analytical model is developed to study the failure mechanism of the VCO.Through SET simulation of all the circuit nodes, the vulnerable nodes of theconventional symmetrical load VCO are got. According to the sensitivity result of VCO,a radiation hardened VCO is improved based on a low cost hardened VCO and theradiation hardened VCO has an improvement in SET sensitivity.3. The radiation-hardened-by-design PLL named RHPLL2is designed andfabricated in130nm CMOS process. Experiment results demonstrat that PLL can workwell in the operating frequency between40MHz to200MHz. Radiation experimentdemonstrates that RHPLL2works well in radiation environment.
Keywords/Search Tags:SET, PLL, CP, VCO, RHBD
PDF Full Text Request
Related items